Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Abstract: The present application discloses a semiconductor structure. The semiconductor structure a top die and a bottom die, and the maximum die size is constrained to reticle dimension. Each die includes (1) core: computation circuits, (2) phy: analog circuit connecting to memory, (3) I/O: analog circuit connecting output elements, (4) SERDES: serial high speed analog circuit, (5) intra-stack connection circuit, and (6) cache memory. This semiconductor structure can be chapleted design for high wafer yield with least tape out masks for cost saving. The intra-stack connection circuit connects the top die and the bottom die in the shortest distance (about tens of micrometers), so as to provide high signal quality and power efficiency.

Abstract: The present application discloses a semiconductor structure and methods for manufacturing semiconductor structures. The semiconductor structure includes a plurality of bottom dies and a top die stacked on the bottom dies. The bottom dies receive power supplies through tiny through silicon vias (TSVs) formed in backside substrates of the bottom dies, while the top die receives power supplies through dielectric vias (TDVs) formed in a dielectric layer that covers the bottom dies. By enabling backside power delivery to the bottom die, more space can be provided for trace routing between stacked dies. Therefore, greater computation capability can be achieved within a smaller chip area with less power loss.

Abstract: A bonded assembly includes an interposer; a semiconductor die that is attached to the interposer and including a planar horizontal bottom surface and a contoured sidewall; a high bandwidth memory (HBM) die that is attached to the interposer; and a dielectric material portion contacting the semiconductor die and the interposer. The contoured sidewall includes a vertical sidewall segment and a non-horizontal, non-vertical surface segment that is adjoined to a bottom edge of the vertical sidewall segment and is adjoined to an edge of the planar horizontal bottom surface of the semiconductor die. The vertical sidewall segment and the non-horizontal, non-vertical surface segment are in contact with the dielectric material portion. The contoured sidewall may provide a variable lateral spacing from the HBM die to reduce local stress in a portion of the HBM die that is proximal to the interposer.

Abstract: A memory management method is provided. The method includes storing an acquired first command into a command queue, and setting a command phase value of the first command according to a current command phase, wherein in response to determining that the first command is a flush command, calculating a command phase count value corresponding to the current command phase, and adjusting the current command phase; selecting a new target command from the command queue, and executing the target command according to a target command phase value of the target command and a corresponding target command phase count value, wherein the target command phase count value which is not a preset value is adjusted; deteiiiiining, according to the adjusted target command phase count value, whether to respond to a host system that an execution of a target flush command corresponding to the target command phase value is completed.

Abstract: A memory management method is provided. The method includes storing an acquired first command into a command queue, and setting a command phase value of the first command according to a current command phase, wherein in response to determining that the first command is a flush command, calculating a command phase count value corresponding to the current command phase, and adjusting the current command phase; selecting a new target command from the command queue, and executing the target command according to a target command phase value of the target command and a corresponding target command phase count value, wherein the target command phase count value which is not a preset value is adjusted; determining, according to the adjusted target command phase count value, whether to respond to a host system that an execution of a target flush command corresponding to the target command phase value is completed.

Abstract: A high access rate flash control provided for accessing more than one flash memory chip having different access timing specifications is disclosed. The controller comprises a read/write(R/W) pulse generator, a R/W delay chain circuit, a sampling delay chain circuit, a bi-directional feedback pad (PAD1), a data bus sampler, and a second pad (PAD 2). In an embodiment, the flash controller using a fix clock to generate synchronized Read/Write pulse which is then appropriated adjusted by the R/W delay chain circuit to provide optimum R/W control signal. The adjusted R/W signal is than outputted by a bi-directional pad to flash memory chips. With the external signal feedback function, the bi-directional pad has associated with the sampling delay chain, the time latency due to pads can be eliminated nearly. Thus, the flash controller can approach high rate to access flash chips.

Abstract: A high access rate flash control provided for accessing more than one flash memory chip having different access timing specifications is disclosed. The controller comprises a read/write (R/W) pulse generator, a R/W delay chain circuit, a sampling delay chain circuit, a bi-directional feedback pad (PAD1), a data bus sampler, and a second pad (PAD2). In an embodiment, the flash controller using a fix clock to generate synchronized Read/Write pulse which is then appropriated adjusted by the R/W delay chain circuit to provide optimum R/W control signal. The adjusted R/W signal is than outputted by a bi-directional pad to flash memory chips. With the external signal feedback function, the bi-directional pad has associated with the sampling delay chain, the time latency due to pads can be eliminated nearly. Thus, the flash controller can approach high rate to access flash chips.