Abstract: The present disclosure provides an electronic wearable device. The electronic wearable device includes a first module having a first contact and a second module having a second contact. The first contact is configured to keep electrical connection with the second contact in moving with respect to each other during a wearing period.

Abstract: A universal serial bus device includes: a core circuit having a first pin and a second pin, and having an input impedance looking into the core circuit from the first pin and the second pin; and a charging control circuit, coupled to the core circuit, arranged for providing a voltage source having a predetermined voltage to one of the first pin and the second pin and for providing a current source having a predetermined current to the other of the first pin and the second pin; wherein the input impedance of the core circuit is configured to make the predetermined voltage and the predetermined current substantially intact when an external charger charges a battery device of the universal serial bus device.

Abstract: A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.

Abstract: A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source.

Abstract: Clock generators are provided. A phase locked loop generates an output clock, a delay line is coupled to an input of the phase locked loop, and a modulation unit integrates an input signal with a constant level to generate a modulation signal controlling the delay line, thereby modulating a phase of a first input clock of the phase locked loop, such that frequency of the output clock is locked at a desired frequency.

Abstract: Spread spectrum generators and methods are disclosed. In one implementation, a spread spectrum clock generator includes a phase locked loop generating an output clock according to a first clock and a second clock; a delay line coupled between the first clock and the phase locked loop; a modulation unit providing a modulation signal to control the delay line thereby modulating phase of the first clock, such that frequency of the output clock generated by the phase locked loop varies periodically; a scaling unit scaling the modulation signal from the modulation unit according to a scaling ratio, and outputting to the delay line; and a calibration unit generating an output signal for controlling the scaling ratio.

Abstract: A termination circuit for a plurality of memories controlled by a controller is provided. The termination circuit includes a plurality of drivers, a plurality of resistors and a plurality of capacitors. Each of the drivers is coupled to the memories via a transmission line. Each of the resistors is coupled to the corresponding driver via the corresponding transmission line. Each of the capacitors is coupled between the corresponding resistor and a reference voltage. The controller is coupled to the memories via the drivers, and the controller provides a specific code to one of the drivers when a quantity of logic “0” and a quantity of logic “1” transmitted to the memories via the transmission line corresponding to the one of the drivers are unbalanced, so as to adjust a termination voltage of the capacitor corresponding to the one of the drivers.

Abstract: A memory controller is provided. The memory controller is powered by first and second power source and includes an input/output pin, a driver circuit, a terminal resistor, and an input buffer. The driver circuit is coupled to the input/output pin and capable of providing to a writing signal to the input/output pin. The terminal resistor is coupled between the input/output pin and the first power source. The input buffer is coupled to the input/output pin and capable of receiving a reading signal from the input/output pin. No terminal resistor is coupled between the input/output pin and the second power source.

Abstract: Spread spectrum clock generators. A phase lock loop generates an output clock according to a first input clock and a second input clock, a delay line is coupled between the first input clock and the phase lock loop. A modulation unit provides a modulation signal to control the delay line thereby modulating phase of the first input clock, such that frequency of the output clock generated by the phase lock loop varies periodically.

Abstract: A phase-locked loop circuit, including: an operating circuit for detecting a difference between a reference signal and a feedback oscillating signal to generate a detected result, and generating a first control signal according to the detected result, an auxiliary circuit for generating a second control signal that is asynchronous with the first control signal, and a controllable oscillator coupled to the operating circuit and the auxiliary circuit for generating an output oscillating signal according to the first control signal and the second control signal, wherein the feedback oscillating signal is derived from the output oscillating signal.

Abstract: A universal serial bus device includes: a core circuit having a first pin and a second pin, and having an input impedance looking into the core circuit from the first pin and the second pin; and a charging control circuit, coupled to the core circuit, arranged for selectively providing a voltage source to one of the first pin and the second pin; wherein the input impedance of the core circuit is configured to make the voltage source substantially intact when the voltage source is coupled to one of the first pin and the second pin.

Abstract: A phase-locked loop circuit, including: an operating circuit for detecting a difference between a reference signal and a feedback oscillating signal to generate a detected result, and generating a first control signal according to the detected result, an auxiliary circuit for generating a second control signal that is asynchronous with the first control signal, and a controllable oscillator coupled to the operating circuit and the auxiliary circuit for generating an output oscillating signal according to the first control signal and the second control signal, wherein the feedback oscillating signal is derived from the output oscillating signal.

Abstract: Clock generators are provided. A phase locked loop generates an output clock, a delay line is coupled to an input of the phase locked loop, and a modulation unit integrates an input signal with a constant level to generate a modulation signal controlling the delay line, thereby modulating a phase of a first input clock of the phase locked loop, such that frequency of the output clock is locked at a desired frequency.

Abstract: Spread spectrum clock generators. A phase lock loop generates an output clock according to a first input clock and a second input clock, a delay line is coupled between the first input clock and the phase lock loop. A modulation unit provides a modulation signal to control the delay line thereby modulating phase of the first input clock, such that frequency of the output clock generated by the phase lock loop varies periodically.

Abstract: A data slicer includes a comparator coupled with an input signal and a reference signal for generating a sliced signal, a waveform generator for generating a calibration signal, a pulse extension device coupled to the comparator and the waveform generator for modifying the duty cycle of the sliced signal or the calibration signal to output, a charge pump coupled between the pulse extension device and a first node for charging and discharging the first node according to the signal output from the pulse extension device, a determining circuit for adjusting the data slicer according to the level change at the first node, and a feedback device coupled between the first node and the comparator for generating the reference signal.

Abstract: An enhanced phase-locked loop (PLL) apparatus having an aligning unit and method are described. The PLL comprises an aligning unit, a phase difference detecting unit, a charge pump, a loop filter, and a voltage-controlled oscillator. The aligning unit receives a hold signal and a reference signal for shifting an edge of the hold signal to generate the gating signal. The phase difference detecting unit detects a phase difference between the reference signal and a feedback signal and outputting an UP signal and a DOWN signal for representing the phase difference. The edge of the hold signal is aligned to an edge of the reference signal. The charge pump generates a current signal based on the UP and DOWN signals. The loop filter is used to generate a control voltage based on the current signal. The voltage-controlled oscillator receives the control voltage and generates an output signal serving as the feedback signal.

Abstract: The invention relates to a PLL apparatus with power saving mode and a method for implementing the same, comprising: a phase detector, a control unit, a charge pump, a loop filter, and a voltage control oscillator. The phase detector generates two detection signals indicating a phase difference between a reference signal and a feedback signal. When the power saving signal is set at a specific logic level, the control unit modifies the two detection signals to be at respective preset levels which keeps the charge pump either charging or discharging an input node of the loop filter to increase/decrease the control voltage outputted by the loop filter. Driven by such a control voltage, the voltage control oscillator generates an oscillating signal at a frequency lower than a normal working frequency so as to achieve power saving objective.

Abstract: A data slicer includes a comparator coupled with an input signal and a reference signal for generating a sliced signal, a waveform generator for generating a calibration signal, a pulse extension device coupled to the comparator and the waveform generator for modifying the duty cycle of the sliced signal or the calibration signal to output, a charge pump coupled between the pulse extension device and a first node for charging and discharging the first node according to the signal output from the pulse extension device, a determining circuit for adjusting the data slicer according to the level change at the first node, and a feedback device coupled between the first node and the comparator for generating the reference signal.