Abstract: A hung structure is provided. The hung structure is adapted to be hung on a fastener. The hung structure includes a hung member and a restriction member. The hung member includes an opening, wherein the opening includes an insertion area and a first slot area, the fastener is adapted to pass through the opening via the insertion area, the fastener is adapted to slide from the insertion area to the first slot area, and when the fastener is in the first slot area, the hung member is supported by the fastener. The restriction member includes an affixed section, an elastic unit and a restriction section. The affixed section is affixed to the hung member. The elastic unit is connected to the affixed section. The restriction section is connected to the elastic unit, wherein the restriction section corresponds to the insertion area.

Abstract: A hung structure is provided. The hung structure is adapted to be hung on a fastener. The hung structure includes a hung member and a restriction member. The hung member includes an opening, wherein the opening includes an insertion area and a first slot area, the fastener is adapted to pass through the opening via the insertion area, the fastener is adapted to slide from the insertion area to the first slot area, and when the fastener is in the first slot area, the hung member is supported by the fastener. The restriction member includes an affixed section, an elastic unit and a restriction section. The affixed section is affixed to the hung member. The elastic unit is connected to the affixed section. The restriction section is connected to the elastic unit, wherein the restriction section corresponds to the insertion area.

Abstract: A method of fabricating a mask ROM is provided, gate dielectric and a plurality of first conductive strips are sequentially formed over a substrate. A first dielectric layer is formed over the substrate and the first conductive strips. The first dielectric layer is patterned to form a plurality of first coding openings. Each first coding opening exposes the first conductive layer. A plurality of first wells is formed in the first conductive layer at the bottom of the first coding openings. A plurality of second conductive strips is formed over the first dielectric layer and inside the first coding openings to connect electrically with corresponding first wells and form a diode memory cell array. Additional diode memory cell arrays may stack over the diode memory cell array to increase device integration.

Abstract: A method of fabricating a mask ROM is provided. gate dielectric and a plurality of first conductive strips are sequentially formed over a substrate. A first dielectric layer is formed over the substrate and the first conductive strips. The first dielectric layer is patterned to form a plurality of first coding openings. Each first coding opening exposes the first conductive layer. A plurality of first wells is formed in the first conductive layer at the bottom of the first coding openings. A plurality of second conductive strips is formed over the first dielectric layer and inside the first coding openings to connect electrically with corresponding first wells and form a diode memory cell array. Additional diode memory cell arrays may stack over the diode memory cell array to increase device integration.