Abstract: An electrical connection defect detection system to detect whether an electrical connection between an under-test pin of an under-test device and a signal line of a circuit board is normal is provided. The electrical connection defect detection system comprises a signal provider providing a test signal to the under-test pin through the signal line, a detection module, an electrode board and a plurality of grounding paths. The electrode board comprises a detection surface to be adapted to a surface of the under-test device opposite to the under-test pin to make the detection module detect a capacitance value associated with the electrode board, the under-test pin and the signal line larger than a threshold value when their connection is normal. The grounding paths are connected to one of not-under-test pin groups respectively to further connect to the ground potential. An electrical connection defect detection method is disclosed herein as well.

Abstract: An electrical connection defect detection device to detect whether an electrical connection between an under-test pin of an under-test device and a signal line of a circuit board is normal is provided. The electrical connection defect detection device comprises a signal provider providing a test signal to the under-test pin through the signal line, a detection module and an electrode board comprising a detection surface and at least one array of through holes. The detection surface contacts a surface of the under-test device to make the detection module detect a capacitance value associated with the electrode board, the under-test pin and the signal line larger than a threshold value when their connection is normal. The through holes are placed along the edges of the electronic board and are electrically connected to a ground potential to perform a capacitive shielding.

Abstract: An apparatus comprises a sensor, a power supply and a measurer. The sensor is placed over the electronic component. The power supply can supply electric power to the printed circuit; thereby the printed circuit is powered on. The measurer can measure a sensing signal through the sensor when the printed circuit is powered on.

Abstract: An electrical connection defect detection system to detect whether an electrical connection between an under-test pin of an under-test device and a signal line of a circuit board is normal is provided. The electrical connection defect detection system comprises a signal provider providing a test signal to the under-test pin through the signal line, a detection module, an electrode board and a plurality of grounding paths. The electrode board comprises a detection surface to be adapted to a surface of the under-test device opposite to the under-test pin to make the detection module detect a capacitance value associated with the electrode board, the under-test pin and the signal line larger than a threshold value when their connection is normal. The grounding paths are connected to one of not-under-test pin groups respectively to further connect to the ground potential. An electrical connection defect detection method is disclosed herein as well.

Abstract: An electrical connection defect detection device to detect whether an electrical connection between an under-test pin of an under-test device and a signal line of a circuit board is normal is provided. The electrical connection defect detection device comprises a signal provider providing a test signal to the under-test pin through the signal line, a detection module and an electrode board comprising a detection surface and at least one array of through holes. The detection surface contacts a surface of the under-test device to make the detection module detect a capacitance value associated with the electrode board, the under-test pin and the signal line larger than a threshold value when their connection is normal. The through holes are placed along the edges of the electronic board and are electrically connected to a ground potential to perform a capacitive shielding.

Abstract: A printed circuit board (PCB) having vias for reducing reflections of input signals includes a first signal layer, a second signal layer, one via, an input signal line arranged on the first signal layer, and an output signal line arranged on the second signal layer. The via further includes a drill hole, a first pad, and a second pad. The first pad is electrically connected with the input signal line, and the second pad is electrically connected with the output signal line. An outer diameter of the first pad is smaller than an outer diameter of the second pad.

Abstract: An apparatus comprises a sensor, a power supply and a measurer. The sensor is placed over the electronic component. The power supply can supply electric power to the printed circuit; thereby the printed circuit is powered on. The measurer can measure a sensing signal through the sensor when the printed circuit is powered on.

Abstract: A layout configuration of a differential pair for a printed circuit board (PCB) having a signal plane is provided. In a preferred embodiment, the layout configuration comprises: a differential pair on the signal plane; a pair of vias abutting the differential pair, and the pair of vias being mutually dissymmetrical about the differential pair; and a distance between the pair of vias along the differential pair being equal to ½ TV, wherein T is a signal rise time, V is a speed of the signal. Therefore, the layout configuration can meet with the requirements of impedance matching, reduce reflection, and improve signal integrity.

Abstract: A method is for controlling an impedance of a via of a printed circuit board. The Via is connected with a trace and includes a drill hole, a pad and an anti-pad. The method includes steps of: building a math model; testing whether an impedance of the via matching with an impedance of the trace; analyzing the impedance of the via if passing the testing; and adjusting parameters of the pad, the anti-pad, and the drill hole if fails testing, and returning to the simulating step, till impedance matching achieved. The method which can efficiently keep signals integrality and increase signal transmission speed.

Abstract: A signal transmission structure includes an aggressor line and a victim line parallel with the aggressor line, and a number of delay portions formed in the victim line. Noise due to crosstalk passing through the delay portion is delayed an amount of time equal to or greater than a rise time of a signal transmitted in the aggressor line. It is of advantage that introducing the delay portions into a victim line of parallel transmission lines can reduce crosstalk caused by mutual inductance and mutual capacitance between the parallel transmission lines.

Abstract: A method is for controlling an impedance of a via of a printed circuit board. The Via is connected with a trace and includes a drill hole, a pad and an anti-pad. The method includes steps of: building a math model; testing whether an impedance of the via matching with an impedance of the trace; analyzing the impedance of the via if passing the testing; and adjusting parameters of the pad, the anti-pad, and the drill hole if fails testing, and returning to the simulating step, till impedance matching achieved. The method which can efficiently keep signals integrality and increase signal transmission speed.

Abstract: A printed circuit board includes improved via for improving signal integrity. The printed circuit board includes a first layer, a second layer, a third layer and a via. The via includes a drill hole, a first pad and a second pad. The first pad is defined in the first layer, and the second pad is defined in the second layer. The drill hole is transversely defined through the first layer and the second layer. A void is defined in the third layer corresponding to the second pad. The PCB attenuates signal reflection when the signal is transmitted through the via improving signal integrity.

Abstract: A multi-layer printed circuit board (PCB) is provided allowing balanced power supply to components requiring large working current. The PCB includes a plurality of layers disposed thereon. A first power area, and a second power area are separately arranged on different layers. The first power area and the second power area vertically aligned within the PCB with generally identical shapes cooperatively provide power to components requiring large working current.

Abstract: A printed circuit board (PCB) having vias for reducing reflections of input signals includes a first signal layer, a second signal layer, one via, an input signal line arranged on the first signal layer, and an output signal line arranged on the second signal layer. The via further includes a drill hole, a first pad, and a second pad. The first pad is electrically connected with the input signal line, and the second pad is electrically connected with the output signal line. An outer diameter of the first pad is smaller than an outer diameter of the second pad.

Abstract: A layout configuration of a differential pair for a printed circuit board (PCB) having a signal plane is provided. In a preferred embodiment, the layout configuration comprises: a differential pair on the signal plane; a pair of vias abutting the differential pair, and the pair of vias being mutually dissymmetrical about the differential pair; and a distance between the pair of vias along the differential pair being equal to ½ TV, wherein T is a signal rise time, V is a speed of the signal. Therefore, the layout configuration can meet with the requirements of impedance matching, reduce reflection, and improve signal integrity.

Abstract: A printed circuit board (PCB) with crosstalk reduction arrangement of differential vias includes a plurality of groups of differential vias, a plurality of signal lines corresponding to the differential vias, and a plurality of layers electrically connected with each other by the differential vias and signal lines. Each group of differential vias comprises a first pair of differential vias and a second pair of differential vias. Straight lines from a center of one of the first pair of vias to a center of another of the first pair of vias and from a center of one of the second pair of differential vias to a center of another of the second pair of differential vias are mutually perpendicularly bisecting.

Abstract: A printed circuit board (PCB) includes a signal layer, a transmission line on the signal layer, a drill hole penetrating the signal layer, and a pad on the signal layer encircling the drill hole, wherein the pad includes an annular region and at least a port extending out from the annular region to connect with the transmission line.

Abstract: An arrangement of differential pairs in a multi-layer printed circuit board is provided for eliminating crosstalk. The arrangement of differential pairs in the multi-layer printed circuit board includes a first differential pair, and a second differential pair. The first differential pair and the second differential pair may each be a driven pair or a victim pair. By properly arranging the first differential pair and the second differential pair, in accordance with the present invention, the resultant crosstalk on the first differential pair induced by the second differential pair, or vice versa, is substantially zero or negligible.

Abstract: A ground plane of a printed circuit board (PCB) includes a number of tiles, wherein the tiles are so regularly arranged that no matter in which way a straight signal line segment is arranged on a signal plane of the PCB, a return current path on the tiles corresponding to the signal line segment is not in a straight line, thereby reducing the difference in impedance of return current paths.

Abstract: An EMI-attenuating air ventilation panel (10, 30) for an electronic device enclosure (100) in accordance with present invention includes an electronically conductive base plate (16) and a plurality of vents (12, 14, 32) defined in the base plate for forming a vents array. Each vent has extruded sidewalls (120, 140, 31) extending from sides therein. In use, the EMI from electronic components within the electronic device enclosure is efficiently attenuated by the sidewalls.