Patents by Inventor Shang-Wei Fang

Shang-Wei Fang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190164949
    Abstract: An integrated circuit structure includes: a first plurality of cell rows extending in a first direction, each of which has a first row height and comprises a plurality of first cells disposed therein; and a second plurality of cell rows extending in the first direction, each of which has a second row height different from the first row height and comprises a plurality of second cells disposed therein. The plurality of first cells comprises a first plurality of active regions each of which continuously extends across the plurality of first cells in the first direction, and wherein the plurality of second cells comprises a second plurality of active regions each of which continuously extends across the plurality of second cells in the first direction.
    Type: Application
    Filed: November 20, 2018
    Publication date: May 30, 2019
    Inventors: Kam-Tou SIO, Jiann-Tyng Tzeng, Jack Liu, Yi-Chuin Tsai, Shang-Wei Fang, Sing-Kai Huang
  • Publication number: 20190164962
    Abstract: An integrated circuit device includes: a first fin structure disposed on a substrate in a first direction; a second fin structure disposed on the substrate and aligned in the first direction; a third fin structure disposed on the substrate and aligned in the first direction; a fourth fin structure disposed on the substrate and aligned in the first direction; and a first conductive line aligned in a second direction arranged to wrap a first portion, a second portion, a third portion, and a fourth portion of the first fin structure, the second fin structure, the third fin structure, and the fourth fin structure respectively. A first distance between the first fin structure and the second fin structure is different from a second distance between the third fin structure and the fourth fin structure.
    Type: Application
    Filed: June 14, 2018
    Publication date: May 30, 2019
    Inventors: KAM-TOU SIO, SHANG-WEI FANG, JIANN-TYNG TZENG, CHEW-YUEN YOUNG
  • Patent number: 8982634
    Abstract: The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.
    Type: Grant
    Filed: January 10, 2014
    Date of Patent: March 17, 2015
    Assignee: eMemory Technology Inc.
    Inventors: Yu-Hsiung Tsai, Yuan-Tai Lin, Ching-Yuan Lin, Chao-Wei Kuo, Shang-Wei Fang, Wein-Town Sun
  • Patent number: 8817543
    Abstract: The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.
    Type: Grant
    Filed: July 11, 2012
    Date of Patent: August 26, 2014
    Assignee: Ememory Technology Inc.
    Inventors: Yu-Hsiung Tsai, Yuan-Tai Lin, Ching-Yuan Lin, Chao-Wei Kuo, Shang-Wei Fang, Wein-Town Sun
  • Publication number: 20140119125
    Abstract: The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.
    Type: Application
    Filed: January 10, 2014
    Publication date: May 1, 2014
    Applicant: eMemory Technology Inc.
    Inventors: Yu-Hsiung Tsai, Yuan-Tai Lin, Ching-Yuan Lin, Chao-Wei Kuo, Shang-Wei Fang, Wein-Town Sun
  • Publication number: 20140016414
    Abstract: The present invention provides a flash memory including a memory cell, a current limiter and a program voltage generator. The memory cell is programmed in response to a program current and a program voltage. The current limiter reflects amount of the program current by a data-line signal, e.g., a data-line voltage. The program voltage generator generates and controls the program voltage in response to the data-line voltage, such that the program current can track to a constant reference current.
    Type: Application
    Filed: July 11, 2012
    Publication date: January 16, 2014
    Applicant: eMemory Technology Inc.
    Inventors: Yu-Hsiung Tsai, Yuan-Tai Lin, Ching-Yuan Lin, Chao-Wei Kuo, Shang-Wei Fang, Wein-Town Sun
  • Patent number: 8467245
    Abstract: A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: June 18, 2013
    Assignee: eMemory Technology Inc.
    Inventors: Shang-Wei Fang, Ying-Je Chen, Hong-Yi Liao, Wein-Town Sun, Yu-Hsiung Tsai, Cheng-Jye Liu
  • Publication number: 20120087192
    Abstract: A method of programming a nonvolatile memory cell which comprises a select transistor and a memory transistor includes applying a preset limit current to a first input of the memory cell, applying a limit voltage to a current limiting circuit electrically connected to a second input of the memory cell, applying a limit voltage to stabilize a voltage drop of the memory cell, and applying a ramped gate voltage to the memory cell to program the memory cell with a preset limited current determined by the current limiting circuit.
    Type: Application
    Filed: December 9, 2011
    Publication date: April 12, 2012
    Inventors: Shang-Wei Fang, Ying-Je Chen, Hong-Yi Liao, Wein-Town Sun, Yu-Hsiung Tsai, Cheng-Jye Liu