Patents by Inventor Shang-Woo Chyou

Shang-Woo Chyou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9697323
    Abstract: A computer system with one or more processors and memory performs a breadth-first-search for an analysis of a digital circuit that includes a plurality of components. The computer system identifies two or more N generation components, initiates processing of the two or more N generation components, and subsequent to initiating the processing of the two or more N generation components, receives results of processing a subset, less than all, of the two or more N generation components. Prior to receiving results of processing all of the N generation components, the computer system identifies one or more N+1 generation components, and initiates processing of the one or more identified N+1 generation components. Subsequently, the computer system receives results of processing at least a subset of the one or more identified N+1 generation components.
    Type: Grant
    Filed: July 28, 2015
    Date of Patent: July 4, 2017
    Assignee: Chyou and Hsu Family Trust 2013
    Inventor: Shang-Woo Chyou
  • Publication number: 20160025809
    Abstract: A computer system with one or more processors and memory performs a breadth-first-search for an analysis of a digital circuit that includes a plurality of components. The computer system identifies two or more N generation components, initiates processing of the two or more N generation components, and subsequent to initiating the processing of the two or more N generation components, receives results of processing a subset, less than all, of the two or more N generation components. Prior to receiving results of processing all of the N generation components, the computer system identifies one or more N+1 generation components, and initiates processing of the one or more identified N+1 generation components. Subsequently, the computer system receives results of processing at least a subset of the one or more identified N+1 generation components.
    Type: Application
    Filed: July 28, 2015
    Publication date: January 28, 2016
    Inventor: Shang-Woo CHYOU
  • Publication number: 20160004803
    Abstract: A computer system with multiple processors and memory identifies a plurality of computation units for a chemical process flowsheet represented by a graph with a plurality of components. The plurality of components includes at least one group of strongly connected components. Each computation unit of the plurality of computation units is either a single component or a group of strongly connected components of the plurality of components. The computer system identifies two or more non-overlapping computation units of the plurality of computation units. All chemical inputs to the two or more non-overlapping computation units have been determined. The computer system processes the two or more non-overlapping computation units at least partially in parallel by processing each computation unit of the two or more non-overlapping computation units using a separate set of one or more processors. The computer system determines process flows for the chemical process flowsheet.
    Type: Application
    Filed: July 7, 2015
    Publication date: January 7, 2016
    Inventor: Shang-Woo CHYOU
  • Patent number: 6405348
    Abstract: A method for static timing analysis of deep sub-micron devices in presence of crosstalk. The present invention provides an efficient platform for fast and accurate static timing verification of large scale transistor and cell level netlists, with coupled interconnects and high switching speeds. The present invention also provides a novel approach to solve the coupled noise problem in static timing verification. The present invention also provides for a method of determining worst case aggressor switching time for a cross-coupled interconnect stage. After the worst case aggressor switching time is determined, the netlist is then resimulated using the worst case aggressor switching time to determine more accuate stage delay and slew of the interconnect stage. The output waveform is recorded and utilized as the input of subsequent stages.
    Type: Grant
    Filed: January 11, 2000
    Date of Patent: June 11, 2002
    Assignee: Synopsys, Inc.
    Inventors: Peivand Fallah-Tehrani, Shang-Woo Chyou