Abstract: A lithium-oxygen primary battery features using a catalyst-free electrolyte. Further, a lithium metal on the negative electrode thereof is decreased to reduce the N/P ratio. Therefore, the lithium-oxygen primary battery of the present invention has a lower cost. The lithium-oxygen primary battery of the present invention has a gravimetric energy density much higher than that of the lithium-oxygen secondary battery.

Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among at least two of the multiple functional blocks. In one implementation, a prior static allocation determines that only a subset of the functional blocks store the data of the given type. In another implementation, each of the functional blocks stores the data of the given type, and when an idle state has occurred, data of the given type is moved between the multiple functional blocks until one or more functional blocks no longer store data of the given type. When a transition to the idle state has occurred, the functional blocks that do not store the data of the given type are transitioned to a sleep state.

Abstract: A system and method for determining power-performance state transition thresholds in a computing system. A processor comprises several functional blocks and a power manager. Each of the functional blocks produces data corresponding to an activity level associated with the respective functional block. The power manager determines activity levels of the functional blocks and compares the activity level of a given functional block to a threshold to determine if a power-performance state (P-state) transition is indicated. The threshold is determined in part on a current P-state of the given functional block. When the current P-state of the given functional block is relatively high, the threshold activity level to transition to a higher P-state is higher than it would be if the current P-state were relatively low. The power manager is further configured to determine the thresholds based in part on one or more of a type of circuit being monitored and a type of workload being executed.

Abstract: An apparatus and method for efficiently managing memory bandwidth within a communication fabric. A computing system includes multiple clients, a display controller, and a communication fabric that transfers data between the multiple clients, the display controller, and a memory subsystem. A control circuit with power management circuitry determines that one or more conditions are satisfied for changing a power-performance state (P-state) of the memory subsystem. The control circuit asserts indications on a sideband interface specifying to the communication fabric that the display controller is to have an increased bandwidth of data transfer between the display controller and the memory subsystem. Using the increased bandwidth provided by the communication fabric, the display controller prefetches display data from a frame buffer of the memory subsystem prior to the P-state change. Afterward, the memory subsystem performs the P-state change and the corresponding training of the memory interface.

Abstract: An apparatus and method for efficiently managing power consumption among multiple, replicated functional blocks of an integrated circuit. An integrated circuit includes multiple, replicated functional blocks that use separate power domains. Data of a given type is stored in an interleaved manner among at least two of the multiple functional blocks. In one implementation, a prior static allocation determines that only a subset of the functional blocks store the data of the given type. In another implementation, each of the functional blocks stores the data of the given type, and when an idle state has occurred, data of the given type is moved between the multiple functional blocks until one or more functional blocks no longer store data of the given type. When a transition to the idle state has occurred, the functional blocks that do not store the data of the given type are transitioned to a sleep state.

Abstract: A method and an apparatus for correcting a proximity effect of an electron beam. An initial dose of the electron beam is preset for each exposed square, and proximity effect energy representing an influence of exposing all exposed squares other than a current exposed square on the current exposed is calculated. A corrected dose of the electron beam for the current exposed square is then calculated, and the corrected dose for each exposed square in the electron beam exposure layout matrix is successively calculated. Then, the above calculation iterates for T times to obtain a final corrected dose of the electron beam for each exposed square.

Abstract: A system and method for determining power-performance state transition thresholds in a computing system. A processor comprises several functional blocks and a power manager. Each of the functional blocks produces data corresponding to an activity level associated with the respective functional block. The power manager determines activity levels of the functional blocks and compares the activity level of a given functional block to a threshold to determine if a power-performance state (P-state) transition is indicated. The threshold is determined in part on a current P-state of the given functional block. When the current P-state of the given functional block is relatively high, the threshold activity level to transition to a higher P-state is higher than it would be if the current P-state were relatively low. The power manager is further configured to determine the thresholds based in part on one or more of a type of circuit being monitored and a type of workload being executed.

Abstract: Systems, apparatuses, and methods for prefetching data by a display controller. From time to time, a performance-state change of a memory are performed. During such changes, a memory clock frequency is changed for a memory subsystem storing frame buffer(s) used to drive pixels to a display device. During the performance-state change, memory accesses may be temporarily blocked. To sustain a desired quality of service for the display, a display controller is configured to prefetch data in advance of the performance-state change. In order to ensure the display controller has sufficient memory bandwidth to accomplish the prefetch, bandwidth reduction circuitry in clients of the system are configured to temporarily reduce memory bandwidth of corresponding clients.

Abstract: Systems, apparatuses, and methods for prefetching data by a display controller. From time to time, a performance-state change of a memory are performed. During such changes, a memory clock frequency is changed for a memory subsystem storing frame buffer(s) used to drive pixels to a display device. During the performance-state change, memory accesses may be temporarily blocked. In order to reduce visual artifacts that may occur while the memory accesses are blocked, a memory subsystem includes a control circuit configured to enable a caching mode which caches display data provided to the display controller. Subsequent requests for display data from the display controller are then serviced using the cached data instead of accessing memory.

Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.

Abstract: Systems, apparatuses, and methods for managing power allocation in a computing system. A system management unit detects a condition indicating a change in power is indicated. Such a change may be detecting an indication that a power change is either required, possible, or requested. In response to detecting a reduction in power is indicated, the system management unit identifies currently executing tasks of the computing system and accesses sensitivity data to determine which of a number of computing units (or power domains) to select for power reduction. Based at least in part on the data, a unit is identified that is determined to have a relatively low sensitivity to power state changes under the current operating conditions. A relatively low sensitivity indicates that a change in power to the corresponding unit will not have as significant an impact on overall performance of the computing system than if another unit was selected. Power allocated for the selected unit is then decreased.

Abstract: A method for manufacturing a continuous stirrup and an apparatus for implementing such method are provided. The method includes placing a planar structure formed of a wave-shaped rebar on a platform, fixing a side of the planar structure and using an elongated mold to abut against the other side of the planar structure to form an intermediate structure, flipping the intermediate structure, and abutting the elongated mold against the side of the planar structure to form a continuous stirrup.

Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.

Abstract: A method for manufacturing a continuous stirrup and an apparatus for implementing such method are provided. The method includes placing a planar structure formed of a wave-shaped rebar on a platform, fixing a side of the planar structure and using an elongated mold to abut against the other side of the planar structure to form an intermediate structure, flipping the intermediate structure, and abutting the elongated mold against the side of the planar structure to form a continuous stirrup.

Abstract: A method for modeling glitch of a logic gate is provided. An input glitch with a glitch width is obtained from the logic gate. The glitch width is scaled by a first scaling factor when the glitch width is greater than or equal to a first threshold width. The glitch width is scaled by a second scaling factor when the glitch width is less than the first threshold width and greater than or equal to a second threshold width. An output glitch with the scaled glitch width is provided for the logic gate. The scaled glitch width is greater than 0. The first threshold width is greater than the second threshold width, and the second scaling factor is smaller than the first scaling factor.

Abstract: A method for modeling glitch of a logic gate is provided. An input glitch with a glitch width is obtained from the logic gate. The glitch width is scaled by a first scaling factor when the glitch width is greater than or equal to a first threshold width. The glitch width is scaled by a second scaling factor when the glitch width is less than the first threshold width and greater than or equal to a second threshold width. An output glitch with the scaled glitch width is provided for the logic gate. The scaled glitch width is greater than 0. The first threshold width is greater than the second threshold width, and the second scaling factor is smaller than the first scaling factor.

Abstract: A method for controlling a walking assistant apparatus includes: scanning a user so as to generate information associated with gait of the user; detecting a torque applied to a torque sensor; estimating a speed of the user based on the information; calculating a compliant motion speed, and a compliant rotational speed; and controlling the motion unit to move at the compliant motion speed and to turn at the compliant rotational speed. This disclosure provides an autonomous obstacle avoidance mechanism; by combining the obstacle avoidance mechanism and the compliance controls, the walking-assistance apparatus is able to help user prevent from collisions with obstacles when walking in an environment with obstacles.

Abstract: A method for controlling a walking assistant apparatus includes: scanning a user so as to generate information associated with gait of the user; detecting a torque applied to a torque sensor; estimating a speed of the user based on the information; calculating a compliant motion speed, and a compliant rotational speed; and controlling the motion unit to move at the compliant motion speed and to turn at the compliant rotational speed. This disclosure provides an autonomous obstacle avoidance mechanism; by combining the obstacle avoidance mechanism and the compliance controls, the walking-assistance apparatus is able to help user prevent from collisions with obstacles when walking in an environment with obstacles.

Abstract: A test bracket includes a base board and two position poles. The position poles are perpendicularly and slidably mounted on the base board opposing each other. Each position pole defines a groove opposing the other position pole. A distance between the position poles is adjusted through sliding the position poles on the base board along the slots. The position poles hold a circuit board to be perpendicularly mounted on the base board by receiving the circuit board in the grooves.

Abstract: An exemplary video graphics array interface tester includes a VGA connector being configured to couple to a VGA interface to be tested and having a plurality of signal pins to output different VGA signals; a load circuit connected to the signal pins of the VGA connector for impedance matching; a selection switch having a plurality of throws corresponding to the signal pins of the VGA connector connected to the signal pins of the VGA connector respectively, and a pole; and a test port connected to the pole of the selection switch for selectively testing one of the VGA signals via selection of the selection switch. Using this tester to detect the VGA interface can guarantee quality and improve efficiency of VGA test.