Abstract: A circuit including an amplifier having an input and an output. The circuit also includes a current-to-voltage amplifier having an input. The circuit further includes a current mirror coupled between the output of the amplifier and the input of the current-to-voltage amplifier. The current mirror is configured to chop current flowing through the first current mirror.

Abstract: A circuit including an amplifier having an input and an output. The circuit also includes a current-to-voltage amplifier having an input. The circuit further includes a current mirror coupled between the output of the amplifier and the input of the current-to-voltage amplifier. The current mirror is configured to chop current flowing through the first current mirror.

Abstract: A circuit including an amplifier having an input and an output. The circuit also includes a current-to-voltage amplifier having an input. The circuit further includes a current mirror coupled between the output of the amplifier and the input of the current-to-voltage amplifier. The current mirror is configured to chop current flowing through the first current mirror.

Abstract: A circuit includes a first transistor having a first control input and first and current terminals. The circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal couples to the first current terminal at a first node. An output stage has a first input, a second input, and an output stage output. The first input couples to the fourth current terminal, and the second input couples to the second current terminal. A resistor has first and second resistor terminals. The first resistor terminal couples to the output stage output, and the second resistor terminal couples to the second control input. A third transistor has a third control input, a fifth current terminal, and a sixth current terminal. The fifth current terminal couples to the first resistor terminal, and the sixth current terminal couples to the second resistor terminal.

Abstract: A circuit includes a first transistor having a first control input and first and current terminals. The circuit also includes a second transistor having a second control input and third and fourth current terminals. The third current terminal couples to the first current terminal at a first node. An output stage has a first input, a second input, and an output stage output. The first input couples to the fourth current terminal, and the second input couples to the second current terminal. A resistor has first and second resistor terminals. The first resistor terminal couples to the output stage output, and the second resistor terminal couples to the second control input. A third transistor has a third control input, a fifth current terminal, and a sixth current terminal. The fifth current terminal couples to the first resistor terminal, and the sixth current terminal couples to the second resistor terminal.

Abstract: A circuit including an amplifier having an input and an output. The circuit also includes a current-to-voltage amplifier having an input. The circuit further includes a current mirror coupled between the output of the amplifier and the input of the current-to-voltage amplifier. The current mirror is configured to chop current flowing through the first current mirror.

Abstract: An amplifier circuit includes an input chopping circuit for chopping first and second input signals, a transconductance stage for amplifying an output of the chopping circuit and applying it to the input of a folded cascode stage, to the input of an un-chopping circuit, and to the input of a chopper-stabilized gain boost amplifier. The output of the un-chopping circuit drives sources of cascode transistors of the folded cascode stage. The gain boost amplifier includes another transconductance stage having another un-chopping circuit coupled to the gate of one of the cascode transistors of the folded cascode stage. The drains of cascode transistors of the folded cascode stage drive a class AB output stage. The amplifier provides both highly linear operation and low 1/f noise.

Abstract: A delta-sigma modulator includes a chopper-stabilized integrator, a quantizer having an input coupled to an output of the integrator, an input signal acquiring circuit controlled by a switched reference feedback circuit and having an output coupled to the input of the integrator, and a frequency-shaped pseudo-random chopper clock signal generator circuit including a pseudo-random sequence generator and producing a frequency-shaped pseudo-random clock signal. Resetting circuitry is coupled to reset inputs of the pseudorandom sequence generator to reset it in synchronization with the digital output of the chopper-stabilized delta-sigma modulator to prevent noise caused by wrap-around operation of the pseudorandom sequence generator. A logic circuit produces chopper clock signals in response to the frequency-shaped pseudo-random clock signal and applies them to various input switches and output switches of the integrator.

Abstract: An amplifier circuit includes an input chopping circuit for chopping first and second input signals, a transconductance stage for amplifying an output of the chopping circuit and applying it to the input of a folded cascode stage, to the input of an un-chopping circuit, and to the input of a chopper-stabilized gain boost amplifier. The output of the un-chopping circuit drives sources of cascode transistors of the folded cascode stage. The gain boost amplifier includes another transconductance stage having another un-chopping circuit coupled to the gate of one of the cascode transistors of the folded cascode stage. The drains of cascode transistors of the folded cascode stage drive a class AB output stage. The amplifier provides both highly linear operation and low 1/f noise.

Abstract: A delta-sigma modulator includes a chopper-stabilized integrator, a quantizer having an input coupled to an output of the integrator, an input signal acquiring circuit controlled by a switched reference feedback circuit and having an output coupled to the input of the integrator, and a frequency-shaped pseudo-random chopper clock signal generator circuit including a pseudo-random sequence generator and producing a frequency-shaped pseudo-random clock signal. Resetting circuitry is coupled to reset inputs of the pseudorandom sequence generator to reset it in synchronization with the digital output of the chopper-stabilized delta-sigma modulator to prevent noise caused by wrap-around operation of the pseudorandom sequence generator. A logic circuit produces chopper clock signals in response to the frequency-shaped pseudo-random clock signal and applies them to various input switches and output switches of the integrator.

Abstract: A delta sigma modulator circuit sums an input signal with a feedback signal representing signal conditions in a group of integrators to provide an input to a quantizer and monitors a signal at the quantizer output to produce a restore signal (RESETA) indicating an instability condition. An integrator includes a dual purpose switch (S3) that is operated together with first and second sampling switches to accomplish an input signal sampling operation and also is operated together with first and second charge transfer switches and an output reset switch to accomplish precise resetting of the integrator, without being directly connected to the amplifier inputs. The dual purpose switch and the reset switch are controlled, respectively, by performing a logical ORing of a first clock signal and the restore signal (RESETA) and by performing a logical ANDing of a non-overlapping second clock signal and the restore signal (RESETA).

Abstract: An analog-to-digital converter (10) includes a high order delta sigma modulator followed by a decimation filter. A monitor circuit (104)coupled to the output of the delta sigma modulator operates to reset its integrators if an unstable condition is detected on the output. The monitor circuit produces first and second jamming signals in response to either a detected overvoltage or undervoltage of the delta sigma modulator input. A logic circuit (SW1) includes a data input coupled to the output of the delta sigma modulator and a data output (89) that jams the input of digital filter (106) with “1” s or “0” s in response to the first or second jamming signal, respectively, to ensure a correct (+) or (−) full scale decimation filter output.

Abstract: A low power Read Only Memory (ROM) bank accessing system with efficient bust muxing is provided. The memory access system includes separate pre-charge and pre-discharge circuits for each bit lines in the ROM bank. In a ROM bank read operation, the pre-discharge circuits and pre-charge circuits are activated and deactivated in accordance with the address of the targeted ROM bank. In an exemplary embodiment, only the pre-charge lines corresponding to the bit-line of the targeted ROM bank are pre-charged prior to the ROM read operation. Similarly, only the pre-discharge circuit corresponding to the bit lines of the targeted ROM bank is deactivated during the ROM read operation, permitting the remaining bit lines from storing residual charge.

Abstract: A low power Read Only Memory (ROM) bank accessing system with efficient bust muxing is provided. The memory access system includes separate pre-charge and pre-discharge circuits for each bit lines in the ROM bank. In a ROM bank read operation, the pre-discharge circuits and pre-charge circuits are activated and deactivated in accordance with the address of the targeted ROM bank. In an exemplary embodiment, only the pre-charge lines corresponding to the bit-line of the targeted ROM bank are pre-charged prior to the ROM read operation. Similarly, only the pre-discharge circuit corresponding to the bit lines of the targeted ROM bank is deactivated during the ROM read operation, permitting the remaining bit lines from storing residual charge.

Abstract: A pipeline ADC includes an input stage and a first group of subsequent stages, wherein the input stage includes a unity gain amplifier having an input for receiving an analog input signal, an output, and first and second comparators each having a first input coupled to the output of the unity gain amplifier. The first comparator has a second input for receiving a first reference voltage an first output, and the second comparator has a second input for receiving a second reference voltage and an output. The input stage includes a full adder coupled to the output of the first comparator, a second input coupled to the output of the second comparator, and an output producing MSB bit information.

Abstract: The voltage swing on an output conductor of a high speed, high dynamic range regulated cascode current mirror is increased by providing a first transistor (M1) of a first conductivity type having a source electrode coupled to a first reference voltage conductor (GND), a gate electrode coupled to a first bias voltage circuit (M5,I1), and a drain coupled to a first conductor (4), a second transistor (M2) of the first conductivity type having a source electrode coupled to the first conductor (4), a gate electrode coupled to a second conductor (3), and a drain electrode coupled to the output conductor (2), and a third transistor (M3) of the first conductivity type having a source electrode coupled to the first reference voltage conductor (GND) and a drain coupled to the second conductor (3). A load circuit (I.sub.2) is coupled between a second reference voltage conductor (V.sub.DD) and the second conductor (3), wherein the third transistor (M3) and the load circuit (I.sub.

Abstract: A delta-sigma modulator includes a chopper-stabilized integrator, a quantizer having an input coupled to an output of the integrator, an input signal acquiring circuit controlled by a switched reference feedback circuit and having an output coupled to the input of the integrator, and a frequency-shaped pseudo-random chopper clock signal generator circuit including a pseudo-random sequence generator and producing a frequency-shaped pseudo-random clock signal. Resetting circuitry is coupled to reset inputs of the pseudo-random sequence generator to reset it in synchronization with the digital output of the chopper-stabilized delta-sigma modulator to prevent noise caused by wrap-around operation of the pseudorandom sequence generator. A logic circuit produces chopper clock signals in response to the frequency-shaped pseudo-random clock signal and applies them to various input switches and output switches of the integrator.