Abstract: A method of forming contact hole is disclosed, including the steps of: providing a semiconductor substrate having a first dielectric layer, a second dielectric layer and a third dielectric layer formed thereon in this order; forming a first contact hole through the third dielectric layer, the second dielectric layer and the first dielectric layer by using an etching process to expose the semiconductor substrate; removing the third dielectric layer; forming a fourth dielectric layer over the second dielectric layer, the fourth dielectric layer filling the first contact hole; forming a second contact hole through the fourth dielectric layer, the second dielectric layer and the first dielectric layer to expose the semiconductor substrate; and removing the fourth dielectric layer. The method is capable of improving the stability of the contact-hole formation process.

Abstract: A method for etching a polysilicon gate is disclosed, wherein the polysilicon gate includes an undoped polysilicon portion and a doped polysilicon portion that is situated on the undoped polysilicon portion. The method includes: obtaining a thickness of the undoped polysilicon portion and a thickness of the doped polysilicon portion by using an optical linewidth measurement device; and etching the undoped polysilicon portion and the doped polysilicon portion by using two respective steps with different parameters, respective etching time for the undoped polysilicon portion and the doped polysilicon portion of every wafer being adjusted in real time by using an advanced process control system. This method enables the doped and undoped polysilicon portions of each polysilicon gate on every wafer to have substantially consistent profiles between each other.

Abstract: The invention provides a measurement of lateral diffusion of implanted ions in the doped well regions of semiconductor devices comprising: designing a test model having active areas, the P-type and N-type doped well regions of the active areas are separated by STI, and the bottom width of the STI is determined; performing multiple processes on the test model comprising the ion implantation process and the tungsten interconnection process to simulate a semiconductor device structure, wherein during the ion implantation process, in the P-type or N-type doped well regions, only the first procedure of the ion implantation process is performed; scanning the test model, obtaining a light-dark pattern of the tungsten interconnects. The present invention is convenient and accessible and can provide reference to optimize the property of the doped well regions of the semiconductor devices and ensure the yield enhancement.

Abstract: The invention provides a SONOS structure, a manufacturing method thereof and a semiconductor device with the SONOS structure. The SONOS structure comprises: a first tunneling oxide layer formed on a substrate, a charge storage silicon nitride layer, a second silicon oxide layer, a thin graded silicon nitride layer having graded Si/N content formed on the second silicon oxide layer, a third silicon oxide layer formed on the thin graded silicon nitride layer, and a polysilicon control gate. The Si/N content ratio of the silicon nitride of the thin graded silicon nitride layer increases gradually, wherein the silicon nitride of the graded silicon nitride layer closer to the second silicon oxide layer contains higher nitride content, and the silicon nitride of the graded silicon nitride layer closer to the third silicon oxide layer contains higher silicon content.

Abstract: The present invention provides a method of forming a nitrogen-free dielectric anti-reflection layer comprising: introducing a reaction gas into the discharge tube until the reaction gas reaching a stable state; introducing the reaction gas into the reaction chamber and then generating a plasma, or generating a plasma and then introducing the reaction gas into the reaction chamber, wherein the time delay occurs between the two processes is utilized to perform the deposition of the nitrogen-free dielectric anti-reflection layer; finally stop introducing the reaction gas and then stop generating the plasma. The method can flexibly control the extinction coefficient and the refractive index of the nitrogen-free dielectric anti-reflection layer so as to obtain a straight photoresist pattern and greatly reduce the photoresist standing waves effect and photoresist poisoning effect.

Abstract: A fabrication method for improving surface planarity after tungsten chemical mechanical polishing (W-CMP) is disclosed. The method forms contact holes and dummy patterns by performing two respective photolithography-and-etching processes to ensure that the dummy patterns have a depth smaller than that of the contact holes. Then the method fills tungsten into the contact holes and dummy patterns and removes the redundant tungsten by a W-CMP process. With such a method, difference of wiring density between areas can be reduced by the dummy patterns, and hence a better surface planarity of the contact hole layer can be achieved. Besides, as the dummy patterns are formed in a pre-metal dielectric layer and their depth is well controlled, tungsten filled in the dummy patterns will not contact with the device area below the pre-metal dielectric layer, and thus will not affect the performance of the device.

Abstract: The present invention disclosed an algorithm of Cu interconnect dummy inserting, including: divide the surface of semiconductor chip into several square windows with an area of A, each of which is non-overlap; perform a logic operation on each square window; and divide the window into two parts: {circle around (1)} the area to-be-inserted; {circle around (2)} the non-inserting area; determine the metal density of the dummy pattern that should be inserted to each square window and the line width; determine the dummy pattern that should be inserted to the windows according to the metal density, line width, the pre-set dummy pattern and the layouting rules. The beneficial effects of the present invention is: avoided the shortcomings of fill density maximization in the rule-based filling method by using reasonable metal density and line width.

Abstract: The invention provides an SONOS structure and a manufacturing method thereof The manufacturing method comprises: forming a tunneling oxide layer on a substrate; depositing a Si-rich silicon nitride layer above the tunneling oxide layer, wherein the Si/N content ratio of the Si-rich silicon nitride layer is constant; depositing a graded silicon nitride layer having graded silicon content above the Si-rich silicon nitride layer; and depositing a blocking oxide layer; wherein the silicon content of the graded silicon nitride layer is reduced in the direction from the Si-rich silicon nitride layer to the blocking oxide layer. According to the present invention, the Si-rich silicon nitride layer provides shallower trapping levels, which is beneficial to trap the charges and improve the programming and erasing speed. Furthermore, the charge retention time increases due to the constrained charges in the deep trapping levels, thus the reliability of the device enhances.

Abstract: A method of depositing phosphosilicate glass (PSG) is disclosed. The method includes a first deposition step for depositing a first PSG layer with a sputtering deposition ratio of 0.10 to 0.16, and a second deposition step for depositing a second PSG layer with a sputtering deposition ratio of 0.18 to 0.22 after the first deposition step. The first PSG layer has a thickness smaller than that of the second PSG layer. With such two-step deposition method, flower pattern having a dramatically reduced size can be formed without occurrence of clipping or formation of sidewall voids in the resultant gate patterns. Specifically, the formed flower pattern has a height reduced by about 50% and a thickness reduced by about 30%.

Abstract: The invention provides a phase shift focus monitor reticle, a manufacturing method thereof, and a method of monitoring focus difference using the phase shift focus monitor reticle. The phase shift focus monitor reticle comprises a shield comprising a plurality of light-transmitting portions with a certain width; and a glass layer positioned on the shield layer comprising a plurality of openings at the light-transmitting portions; wherein the width of the openings is half of the width of the light-transmitting portions; the depth of the openings is n*?/(N?1), wherein ? is the wavelength of the lights incident on the phase shift focus monitor reticle in air, N is the refractive index of the glass layer, n is a positive integer. The invention can be applied to thicker photoresist and different process machines.

Abstract: The present invention provides a method and model for monitoring the pretreatment process of a low-k block layer. The method comprises measuring film parameters of the film formed on the silicon substrate after applying the pretreatment process for different time periods; creating a statistical process control curve according to the film parameters; setting a SPC control limit; determining the pretreatment process normal when the data point of measurement in the SPC curve is within the control limit while determining the pretreatment process abnormal when the data point of measurement in the SPC curve exceeds the control limit. According to the present invention, the failure of the pretreatment process can be prevented to improve the product reliability and stability.

Abstract: The invention provides a semiconductor yield management system. The system comprises an electronic data collection module and an execution module, the execution module comprises a plurality of execution sub-modules in sequence to perform executions on an object successively, the of the execution sub-modules comprises an execution section and an inspection section; the execution section of the execution sub-module is connected with the inspection section of the preceding execution sub-module except for the first execution sub-module; the inspection section of the execution sub-module is connected with the execution section of the subsequent execution sub-module except for the last execution sub-module; the inspection module of the execution sub-module is connected with the electronic data collection module. According to the semiconductor yield management system, the potential not-good wafers can be recorded, analyzed and distributed to the corresponding execution module, which realizes the risk minimization.

Abstract: The invention provides a method for monitoring devices in semiconductor process comprising: Step a, designing a sampling plan with fixed sample size before the beginning of the semiconductor process; Step b, determining whether to sample the wafers according to the sampling plan and dispatching the wafers to be sampled to each process device before the beginning of the process step, wherein the process device is used for performing the process step; Step c, performing the process step; Step d, sampling the wafers according to the sampling plan, and performing in-line inspection to the sampled wafers according to the sampling results; Step e, repeating Step b to Step d until all the process steps are completed; Step f, performing e-test to all the wafers. According to the method, the potential risk during the semiconductor process can be minimized through the coordination of the sampling plan and the dynamic risk flag.

Abstract: The invention provides a temperature balancing device for a projection objective of a lithography machine. The device comprises at least one temperature sensor, at least one heat-absorbing light-transmitting layer and an objective temperature balancing control unit, wherein the temperature sensor is disposed adjacent to the projection objective for sensing the temperature difference of the projection objective in different areas; the heat-absorbing light-transmitting layer is positioned below the projection objective for absorbing radiation energy in the laser beams transmitted from the lithography machine and transmitting the laser beams; and the objective temperature balancing control unit is used for controlling the absorption degree and light transmission degree of the heat-absorbing light-transmitting layer according to the temperature difference sensed by the temperature sensor. The invention also discloses a method for balancing temperature of a projection objective of a lithography machine.