Abstract: An array base plate includes a substrate; a plurality of sub-pixels; and a plurality of gate lines and a plurality of data lines, wherein the plurality of gate lines intersect with the plurality of data lines, each of the sub-pixels is located at a position limited by two adjacent gate lines and two adjacent data lines, and each of the sub-pixels includes a pixel driving circuit and a light emitting device that are connected; wherein the pixel driving circuit includes: a drive module and a first control module, the pixel driving circuit further includes an auxiliary anode, the auxiliary anode is located between the anode and the substrate, and the auxiliary anode is electrically connected to the anode; the first power signal line includes a first part and a second part that are electrically connected.

Abstract: A display substrate includes an array substrate including pixels and pixel driving circuits. A pixel driving circuit includes a driving sub-circuit and a storage sub-circuit. The storage sub-circuit includes: a first capacitor coupled to a first node and a second node, and a second capacitor coupled to the second node and a first voltage signal terminal. The driving sub-circuit is configured to generate a driving current under control of the storage sub-circuit and transmit the driving current to a light-emitting device. In a direction perpendicular to the array layer, the first plate, the second plate, the third plate and the fourth plate have an overlapping region therebetween.

Abstract: Provided is a gate drive circuit, including a plurality of shift registers and buffers in cascade, wherein each of the shift registers is configured to output a first gate scanning signal stage by stage according to a preset scanning timing; and each of the buffers is configured to perform waveform inversion on the first gate scanning signal for a plurality of times to convert the first gate scanning signal into a second gate scanning signal, wherein falling edge time of the second gate scanning signal is less than falling edge time of the first gate scanning signal.

Abstract: A driving circuit, a driving method, a display device, and a display control method are provided. The driving circuit includes multi-stage driving units and an on/off control circuit. Each of the driving units includes an input end and a driving signal output end, and each of the driving units is configured for outputting a corresponding driving signal via the driving signal output end according to an input signal provided by the input end. The input end of a first-stage driving unit is electrically connected to a start signal end. The on/off control circuit is electrically connected to an on/off control end and input ends of the multi-stage driving units, and configured for controlling the electric connection or electric disconnection of the input ends of the multi-stage driving units under the control of an on/off control signal provided by the on/off control end.

Abstract: An array base plate includes a silicon substrate including multiple cascaded EOA units disposed at a peripheral area; the EOA units are electrically connected to a pixel driving unit; each EOA unit includes an input circuit transmitting a signal input by a light-emitting control signal input line to the EOA unit; a first control circuit transmitting a second power signal input by a second power signal line to a first node, and transmitting a first power signal input by a first power signal line to a second node; a second control circuit transmitting a second clock signal to a third node or transmitting the second power signal to the third node; a pull-up circuit transmitting the first power signal to a light-emitting control signal output line, and a pull-down circuit transmitting the second power signal to the light-emitting control signal output line.

Abstract: A driving circuit, a driving method, a display device, and a display control method are provided. The driving circuit includes multi-stage driving units and an on/off control circuit. Each of the driving units includes an input end and a driving signal output end, and each of the driving units is configured for outputting a corresponding driving signal via the driving signal output end according to an input signal provided by the input end. The input end of a first-stage driving unit is electrically connected to a start signal end. The on/off control circuit is electrically connected to an on/off control end and input ends of the multi-stage driving units, and configured for controlling the electric connection or electric disconnection of the input ends of the multi-stage driving units under the control of an on/off control signal provided by the on/off control end.

Abstract: An array base plate includes a silicon substrate including multiple cascaded EOA units disposed at a peripheral area; the EOA units are electrically connected to a pixel driving unit; each EOA unit includes an input circuit transmitting a signal input by a light-emitting control signal input line to the EOA unit; a first control circuit transmitting a second power signal input by a second power signal line to a first node, and transmitting a first power signal input by a first power signal line to a second node; a second control circuit transmitting a second clock signal to a third node or transmitting the second power signal to the third node; a pull-up circuit transmitting the first power signal to a light-emitting control signal output line, and a pull-down circuit transmitting the second power signal to the light-emitting control signal output line.