Abstract: A power conversion circuit and a power conversion circuit control method. The power conversion circuit determines polarity of an alternating current voltage by using a PFC circuit controller, determines, based on a current of an inductor, a signal for controlling a secondary switch to be turned off, determines, based on a voltage at a midpoint of a series connection between a switching transistor S1 and a switching transistor S2, a signal for controlling the secondary switch to be turned on again and a signal for controlling a primary switch to be turned off, and performs PWM control on the switching transistor S1 and the switching transistor S2.

Abstract: This application provides a voltage converter and a power supply system. In one example, a voltage converter includes a voltage conversion circuit and a controller. The voltage conversion circuit is configured to receive an input voltage from a power supply, and perform buck conversion on the input voltage to obtain an output voltage, to supply power to a load. The controller is configured to: when the voltage conversion circuit is in a first state, control the output voltage by controlling a level conduction signal of the voltage conversion circuit, to supply power to the load. The first state is a state in which a value of a duty ratio of the voltage conversion circuit is greater than or equal to a preset duty ratio value. The first state includes a first saturation state and a second saturation state.

Abstract: A power supply apparatus includes a totem-pole power factor correction (PFC) circuit and a control apparatus, and the totem-pole PFC circuit includes a first switching transistor and a second switching transistor. The control apparatus includes a controller and a dead time detection circuit, and the dead time detection circuit includes a detection capacitor and a detection resistor. A first end of the detection capacitor is connected to a first reference point, a second end of the detection capacitor is connected to a first end of the detection resistor, and a second end of the detection resistor is grounded. The controller is configured to, respectively, control an on/off status of the first switching transistor and an on/off status of the second switching transistor based on a voltage of the detection resistor and polarity of a voltage input by an alternating current input source.

Abstract: A method for controlling a totem-pole PFC circuit. When an alternating current of an input end of a totem-pole PFC circuit is in a positive half period, if a previous switching period is less than specified duration, after charging of a PFC inductor is completed, a switch that enables the PFC inductor to be discharged is first delayed for specified threshold duration, and then the switch that enables the PFC inductor to be discharged is turned on, so that the switch that enables the PFC inductor to be discharged is turned on only once. In an existing PFC application, when an input voltage is in a positive half period, a switch that enables a PFC inductor to be discharged needs to be turned on twice.

Abstract: A noise suppression method and apparatus for a totem pole power factor correction (PFC) circuit and an electronic device are provided. In response to a determination that an alternating current of the totem pole PFC circuit is switched at a zero crossing, a control signal is sent to a switch that enables a PFC inductor in the totem pole PFC circuit to charge or discharge. After the switch is turned off for a first period of time, the switch is turned on again for a second period of time.

Abstract: The control system includes a PFC circuit and a sampling control circuit, and the PFC circuit includes an inductor, a first power supply drive circuit, and a first bridge arm and a second bridge arm that are connected in parallel, and a first bridge arm midpoint is a serial connection point between a first upper bridge arm and a first lower bridge arm of the first bridge arm. The sampling control circuit is configured to control, based on voltages of two ends of an alternating current power supply, the first lower bridge arm to be turned on, so that the first power supply drive circuit starts charging. The sampling control circuit is further configured to: when charging duration of the first power supply drive circuit reaches first target duration, control the first lower bridge arm to be turned off, so that the first power supply drive circuit completes charging.

Abstract: A power supply apparatus includes a totem-pole power factor correction (PFC) circuit and a control apparatus, and the totem-pole PFC circuit includes a first switching transistor and a second switching transistor. The control apparatus includes a controller and a dead time detection circuit, and the dead time detection circuit includes a detection capacitor and a detection resistor. A first end of the detection capacitor is connected to a first reference point, a second end of the detection capacitor is connected to a first end of the detection resistor, and a second end of the detection resistor is grounded. The controller is configured to, respectively, control an on/off status of the first switching transistor and an on/off status of the second switching transistor based on a voltage of the detection resistor and polarity of a voltage input by an alternating current input source.

Abstract: A power conversion circuit and a power conversion circuit control method. The power conversion circuit determines polarity of an alternating current voltage by using a PFC circuit controller, determines, based on a current of an inductor, a signal for controlling a secondary switch to be turned off, determines, based on a voltage at a midpoint of a series connection between a switching transistor S1 and a switching transistor S2, a signal for controlling the secondary switch to be turned on again and a signal for controlling a primary switch to be turned off, and performs PWM control on the switching transistor S1 and the switching transistor S2.

Abstract: A noise suppression method and apparatus for a totem pole power factor correction (PFC) circuit and an electronic device are provided. In response to a determination that an alternating current of the totem pole PFC circuit is switched at a zero crossing, a control signal is sent to a switch that enables a PFC inductor in the totem pole PFC circuit to charge or discharge. After the switch is turned off for a first period of time, the switch is turned on again for a second period of time.

Abstract: A method for controlling a totem-pole PFC circuit. When an alternating current of an input end of a totem-pole PFC circuit is in a positive half period, if a previous switching period is less than specified duration, after charging of a PFC inductor is completed, a switch that enables the PFC inductor to be discharged is first delayed for specified threshold duration, and then the switch that enables the PFC inductor to be discharged is turned on, so that the switch that enables the PFC inductor to be discharged is turned on only once. In an existing PFC application, when an input voltage is in a positive half period, a switch that enables a PFC inductor to be discharged needs to be turned on twice.

Abstract: A pin state configuration circuit, a method for configuring pin states and an electronic device for configuring pin states are provided. The pin state configuration circuit includes a configured resistor load, a voltage sampling unit, and a comparator. The voltage sampling unit supplies a reference voltage to the configured resistor load by using a first or second configuration pin, and respectively samples voltages of the first and second configuration pins. The comparator calculates a first voltage ratio based on the voltage of the first configuration pin and the voltage of the second configuration pin, calculates a second voltage ratio based on the voltage of the first configuration pin and the voltage of the second configuration pin, and determines a corresponding pin configuration state based on the first and second voltage ratios. In this way, N×N pin configuration states may be obtained by configuring two configuration pins.

Abstract: A pin state configuration circuit, a method for configuring pin states and an electronic device for configuring pin states are provided. The pin state configuration circuit includes a configured resistor load, a voltage sampling unit, and a comparator. The voltage sampling unit supplies a reference voltage to the configured resistor load by using a first or second configuration pin, and respectively samples voltages of the first and second configuration pins. The comparator calculates a first voltage ratio based on the voltage of the first configuration pin and the voltage of the second configuration pin, calculates a second voltage ratio based on the voltage of the first configuration pin and the voltage of the second configuration pin, and determines a corresponding pin configuration state based on the first and second voltage ratios. In this way, N×N pin configuration states may be obtained by configuring two configuration pins.

Abstract: The control system includes a PFC circuit and a sampling control circuit, and the PFC circuit includes an inductor, a first power supply drive circuit, and a first bridge arm and a second bridge arm that are connected in parallel, and a first bridge arm midpoint is a serial connection point between a first upper bridge arm and a first lower bridge arm of the first bridge arm. The sampling control circuit is configured to control, based on voltages of two ends of an alternating current power supply, the first lower bridge arm to be turned on, so that the first power supply drive circuit starts charging. The sampling control circuit is further configured to: when charging duration of the first power supply drive circuit reaches first target duration, control the first lower bridge arm to be turned off, so that the first power supply drive circuit completes charging.