Patents by Inventor Shankar Balachandran
Shankar Balachandran has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230409481Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.Type: ApplicationFiled: May 19, 2023Publication date: December 21, 2023Applicant: Intel CorporationInventors: Sreenivas Subramoney, Stanislav Shwartsman, Anant Nori, Shankar Balachandran, Elad Shtiegmann, Vineeth Mekkat, Manjunath Shevgoor, Sourabh Alurkar
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Patent number: 11693780Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.Type: GrantFiled: August 2, 2021Date of Patent: July 4, 2023Assignee: Intel CorporationInventors: Sreenivas Subramoney, Stanislav Shwartsman, Anant Nori, Shankar Balachandran, Elad Shtiegmann, Vineeth Mekkat, Manjunath Shevgoor, Sourabh Alurkar
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Publication number: 20230205692Abstract: Apparatus and method for leveraging simultaneous multithreading for bulk compute operations. For example, one embodiment of a processor comprises: a plurality of cores including a first core to simultaneously process instructions of a plurality of threads; a cache hierarchy coupled to the first core and the memory, the cache hierarchy comprising a Level 1 (L1) cache, a Level 2 (L2) cache, and a Level 3 (L3) cache; and a plurality of compute units coupled to the first core including a first compute unit associated with the L1 cache, a second compute unit associated with the L2 cache, and a third compute unit associated with the L3 cache, wherein the first core is to offload instructions for execution by the compute units, the first core to offload instructions from a first thread to the first compute unit, instructions from a second thread to the second compute unit, and instructions from a third thread to the third compute unit.Type: ApplicationFiled: December 23, 2021Publication date: June 29, 2023Inventors: ANANT NORI, RAHUL BERA, SHANKAR BALACHANDRAN, JOYDEEP RAKSHIT, Om Ji OMER, SREENIVAS SUBRAMONEY, AVISHAII ABUHATZERA, BELLIAPPA KUTTANNA
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Publication number: 20230183917Abstract: The present disclosure provides fabrics comprising graphene and/or its derivative(s), wherein said graphene comprising fabrics are characterized by at least three features selected from anti-microbial, antistatic, wicking, thermal cooling, anti-odour and ultraviolet protection. Said graphene comprising fabrics of the present disclosure show several further beneficial properties including but not limited to good/excellent washing fastness, rubbing fastness, perspiration fastness, sublimation fastness and light fastness.Type: ApplicationFiled: February 23, 2021Publication date: June 15, 2023Inventors: Joseph Berkmans AMIRTHASAMY, Animesh LAHA, Vivek Prabhakar RAJE, Debarati Roy CHOUDRY, Mahendra Kumar SHUKLA, Prateek NIGAM, Sushant Suresh REKHI, Vijai Shankar BALACHANDRAN, Moumita NANDY, Kaustav GOSWAMI
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Publication number: 20220100514Abstract: Techniques for processing loops are described. An exemplary apparatus at least includes decoder circuitry to decode a single instruction, the single instruction to include a field for an opcode, the opcode to indicate execution circuitry is to perform an operation to configure execution of one or more loops, wherein the one or more loops are to include a plurality of configuration instructions and instructions that are to use metadata generated by ones of the plurality of configuration instructions; and execution circuitry to perform the operation as indicated by the opcode.Type: ApplicationFiled: December 26, 2020Publication date: March 31, 2022Inventors: Anant NORI, Shankar BALACHANDRAN, Sreenivas SUBRAMONEY, Joydeep RAKSHIT, Vedvyas SHANBHOGUE, Avishaii ABUHATZERA, Belliappa KUTTANNA
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Publication number: 20210365377Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.Type: ApplicationFiled: August 2, 2021Publication date: November 25, 2021Applicant: Intel CorporationInventors: Sreenivas Subramoney, Stanislav Shwartsman, Anant Nori, Shankar Balachandran, Elad Shtiegmann, Vineeth Mekkat, Manjunath Shevgoor, Sourabh Alurkar
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Patent number: 11080194Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.Type: GrantFiled: December 27, 2018Date of Patent: August 3, 2021Assignee: Intel CorporationInventors: Sreenivas Subramoney, Stanislav Shwartsman, Anant Nori, Shankar Balachandran, Elad Shtiegmann, Vineeth Mekkat, Manjunath Shevgoor, Sourabh Alurkar
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Patent number: 10846084Abstract: Implementations of the disclosure implement timely and context triggered (TACT) prefetching that targets particular load IPs in a program contributing to a threshold amount of the long latency accesses. A processing device comprising an execution unit; and a prefetcher circuit communicably coupled to the execution unit is provided. The prefetcher circuit is to detect a memory request for a target instruction pointer (IP) in a program to be executed by the execution unit. A trigger IP is identified to initiate a prefetch operation of memory data for the target IP. Thereupon, an association is determined between memory addresses of the trigger IP and the target IP. The association comprising a series of offsets representing a path between the trigger IP and an instance of the target IP in memory. Based on the association, an offset from the memory address of the trigger IP to prefetch the memory data is produced.Type: GrantFiled: January 3, 2018Date of Patent: November 24, 2020Assignee: Intel CorporationInventors: Anant Vithal Nori, Sreenivas Subramoney, Shankar Balachandran, Hong Wang
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Publication number: 20200210339Abstract: System and method for prefetching pointer-referenced data. A method embodiment includes: tracking a plurality of load instructions which includes a first load instruction to access a first data that identifies a first memory location; detecting a second load instruction which accesses a second memory location for a second data, the second memory location matching the first memory location identified by the first data; responsive to the detecting, updating a list of pointer load instructions to include information identifying the first load instruction as a pointer load instruction; prefetching a third data for a third load instruction prior to executing the third load instruction; identifying the third load instruction as a pointer load instruction based on information from the list of pointer load instructions and responsively prefetching a fourth data from a fourth memory location, wherein the fourth memory location is identified by the third data.Type: ApplicationFiled: December 27, 2018Publication date: July 2, 2020Inventors: Sreenivas Subramoney, Stanislav Shwartsman, Anant Nori, Shankar Balachandran, Elad Shtiegmann, Vineeth Mekkat, Manjunath Shevgoor, Sourabh Alurkar
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Patent number: 10472241Abstract: The present disclosure relates to a process for the synthesis of highly crystalline carbon nanotubes (CNTs). Processes known in the art employ post-synthesis processes such as oxidation or hydrothermal treatment to produce CNTs with high crystallinity. The present disclosure produces highly crystalline CNTs at a low growth temperature and without hydrogen flow condition and without employing any post-production process. The process disclosed in the present disclosure produces CNTs having a crystallinity greater than 5 which makes them suitable for various industrial applications.Type: GrantFiled: October 6, 2016Date of Patent: November 12, 2019Assignee: Reliance Industries LimitedInventors: Gopal Krishna Goswami, Swanand Dilip Patil, Sreekumar Thaliyil Veedu, Vijai Shankar Balachandran
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Publication number: 20190205135Abstract: Implementations of the disclosure implement timely and context triggered (TACT) prefetching that targets particular load IPs in a program contributing to a threshold amount of the long latency accesses. A processing device comprising an execution unit; and a prefetcher circuit communicably coupled to the execution unit is provided. The prefetcher circuit is to detect a memory request for a target instruction pointer (IP) in a program to be executed by the execution unit. A trigger IP is identified to initiate a prefetch operation of memory data for the target IP. Thereupon, an association is determined between memory addresses of the trigger IP and the target IP. The association comprising a series of offsets representing a path between the trigger IP and an instance of the target IP in memory. Based on the association, an offset from the memory address of the trigger IP to prefetch the memory data is produced.Type: ApplicationFiled: January 3, 2018Publication date: July 4, 2019Inventors: Anant Vithal Nori, Sreenivas Subramoney, Shankar Balachandran, Hong Wang
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Publication number: 20180290889Abstract: The present disclosure relates to a process for the synthesis of highly crystalline carbon nanotubes (CNTs). Processes known in the art employ post-synthesis processes such as oxidation or hydrothermal treatment to produce CNTs with high crystallinity. The present disclosure produces highly crystalline CNTs at a low growth temperature and without hydrogen flow condition and without employing any post-production process. The process disclosed in the present disclosure produces CNTs having a crystallinity greater than 5 which makes them suitable for various industrial applications.Type: ApplicationFiled: October 6, 2016Publication date: October 11, 2018Applicant: Reliance Industries LimitedInventors: Gopal Krishna Goswami, Swanand Dilip Patil, Sreekumar Thaliyil Veedu, Vijai Shankar Balachandran