Abstract: In the monitoring domain, event management can deal with the monitoring of behavioural changes for any type of entity. Normally, the event management requires a lot of human intervention to generate a set of rules which results in adding effort and cost. A method and system for managing a plurality of events using automated rule generation has been provided. The system automatically generates a set of rules by studying the trend of incoming events over a period of time by computing moving percentile, thereby removing the need of human intervention to define rules for alert generation. The reported alerts are more specific and accurate, since the trend of incoming data is used to define the rules for alert generation. Further the method also provides the provision for the resolving the generated alerts either manually or automatically.

Abstract: A timer counter with multiple timers in a pipelined architecture in which the multiple timers are serviced in the pipeline. The timer counter includes a control unit having a first control section and a second control section for sequencing the servicing of each of the multiple timers in a pipeline. The first and second control sections provide a pipeline sequence of the total required service of the timer counter. The pipeline architecture allows the multiple timers to be serviced in a pipeline without increasing the overall number of clocks.

Abstract: A microprocessor system integrated on a chip having one or more address generation devices, at least one memory location, and at least one peripheral unit. The address path is divided into two portions having a first logic unit conditioning the address from the one or more address generation devices on the first portion of the address path for gating onto the second portion of the address path. The first logic unit converts a single 16 bit address location into two 8 bit address locations. The first logic unit maintains a first address on the second address path when the CPU is in a next address pipeline mode. A second logic unit selects a memory architecture so that the system can address DRAM units having a various number of rows and/or columns.

Abstract: A microprocessor system having a first read path from memory and a second read path from peripheral units and an isolation buffer to isolate the first read path from the second read path. The system also has a first write path to memory and a second write path to peripheral units and an isolation buffer to isolate the first write path from the second write path. The isolation buffers also isolate the write paths from the read paths. Also included is a monitoring path between the peripherals and an external bus to allow program monitoring of data in the peripheral units.

Abstract: A configurable emulator system for emulating a microcontroller device architecture selected from a plurality of microcontroller device architectures is provided. The configurable emulator includes a master microcontroller emulator comprising at least one functional block that responds to a mode select input signal for designating the functional block as having a desired integrated circuit feature. The master microcontroller emulator includes means responsive to control code for executing the control code. A configuration mode selector responds to an external input signal by asserting a configuration flag. Bus selector means responds to the assertion of the configuration flag by transferring configuration data provided at a bus selector input to a configuration data output. The bus selector transfers control code provided at the bus selector input to the master microcontroller emulator via a control code output when the configuration flag is not asserted.

Abstract: Apparatus for serially programming a microcontroller's on-chip EPROM includes mode decode logic that responds to operating mode input signals by generating corresponding operating mode signals, including an EPROM mode signal. An upper byte address shift register serially receives a most significant address portion of an EPROM address in response to a shift clock signal and provides the most significant address portion as an upper byte parallel output. A lower byte address shift register serially receives a least significant address portion of the EPROM address in response to the shift clock and provides the least significant address portion as a lower byte parallel output. A memory address register loads the upper and lower byte parallel outputs from the upper and lower byte address shift registers, respectively, and provides an EPROM address output in response to a load signal. An EPROM memory element responds to the EPROM address by providing access to a storage element specified by the EPROM address.