Patents by Inventor Shankar Ganesh Ramasubramanian
Shankar Ganesh Ramasubramanian has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220392519Abstract: Methods and apparatus for opportunistic full duplex DRAM for tightly coupled compute die and memory die. A memory controller includes one or more memory channel input-output (IO) interfaces having sets of read data (RdDQ) lines and write data (WrDQ) lines, and includes logic to implement concurrent read and write operations utilizing the RdDQ lines and WrDQ lines. A memory channel IO interface may be coupled to one or more memory devices such as DRAM DIMMs or DRAM/SDRAM dies having a mating IO interface, such as using through-silicon vias (TSVs) and die-to-die interconnects. Circuitry in a memory device or die includes a macro block of IO drivers coupled to the memory channel IO circuitry via a macro interface supporting full duplex operations. IO drivers in a macro block may be connected to memory banks using half-duplex bi-direction links to different banks or full duplex links to the same bank.Type: ApplicationFiled: August 19, 2022Publication date: December 8, 2022Inventors: Randy B. OSBORNE, Christopher P. MOZAK, Shankar Ganesh RAMASUBRAMANIAN
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Patent number: 11281616Abstract: A device includes a driver circuit to send data bits onto a data bus that is partitioned into a DC component and an AC component. The driver circuit is to, for some data bits, retrieve a value of a DC power ratio of the data bus. The driver circuit is further to determine, using the value of the DC power ratio, a first value for a first portion of total power to be dissipated over the DC component to transmit the data bits, and determine, using one minus the value of the DC power ratio, a second value for a second portion of total power to be dissipated over the AC component to transmit the data bits. The driver circuit is to determine whether to send the data bits onto the data bus using data bus inversion dependent on a combination of the first value and the second value.Type: GrantFiled: October 24, 2019Date of Patent: March 22, 2022Assignee: Intel CorporationInventors: Melin Dadual, Vivek Joy Kozhikkottu, Shankar Ganesh Ramasubramanian
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Patent number: 11216386Abstract: Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.Type: GrantFiled: September 26, 2019Date of Patent: January 4, 2022Assignee: Intel CorporationInventors: Vivek Kozhikkottu, Suresh Chittor, Esha Choukse, Shankar Ganesh Ramasubramanian
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Patent number: 10936507Abstract: In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.Type: GrantFiled: March 28, 2019Date of Patent: March 2, 2021Assignee: Intel CorporationInventors: Vivek Kozhikkottu, Esha Choukse, Shankar Ganesh Ramasubramanian, Melin Dadual, Suresh Chittor
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Patent number: 10862622Abstract: Embodiments may relate to a processor to an electronic device that includes an error correction code (ECC) encoder that is to perform ECC encoding on aa data message to generate an ECC encoded data message. The electronic device may further include a data bus inversion (DBI) encoder communicatively coupled with the ECC encoder, wherein the DBI encoder is to perform DBI encoding on the ECC encoded data message to generate a DBI encoded data message. Other embodiments may be described or claimed.Type: GrantFiled: May 23, 2019Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Vivek Joy Kozhikkottu, Shankar Ganesh Ramasubramanian, Dinesh Somasekhar, Melin Dadual
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Patent number: 10860419Abstract: Systems and methods related to data encoders that can perform error detection or correction. The encoders and decoders may minimize the addition of errors due to aliasing in error correction codes by implementing operators associated with reduced aliasing parity generating or reduced aliasing error checking matrices.Type: GrantFiled: December 28, 2018Date of Patent: December 8, 2020Assignee: Intel CorporationInventors: Dinesh Somasekhar, Wei Wu, Shankar Ganesh Ramasubramanian, Vivek Kozhikkottu, Melin Dadual
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Patent number: 10853300Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.Type: GrantFiled: March 31, 2017Date of Patent: December 1, 2020Assignee: Intel CorporationInventors: Vivek Kozhikkottu, Shankar Ganesh Ramasubramanian, Kon-Woo Kwon, Dinesh Somasekhar
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Publication number: 20200310979Abstract: In one embodiment, an apparatus includes: a page table circuit to receive a virtual address and to generate at least a portion of a physical address therefrom; and a mapping rule table coupled to the page table circuit, the mapping rule table to receive mapping metadata of a page of a system memory and, based on the mapping metadata, output a mapping rule for the page. Other embodiments are described and claimed.Type: ApplicationFiled: March 28, 2019Publication date: October 1, 2020Inventors: Vivek Kozhikkottu, Esha Choukse, Shankar Ganesh Ramasubramanian, Melin Dadual, Suresh Chittor
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Publication number: 20200285599Abstract: A device includes a driver circuit to send data bits onto a data bus that is partitioned into a DC component and an AC component. The driver circuit is to, for some data bits, retrieve a value of a DC power ratio of the data bus. The driver circuit is further to determine, using the value of the DC power ratio, a first value for a first portion of total power to be dissipated over the DC component to transmit the data bits, and determine, using one minus the value of the DC power ratio, a second value for a second portion of total power to be dissipated over the AC component to transmit the data bits. The driver circuit is to determine whether to send the data bits onto the data bus using data bus inversion dependent on a combination of the first value and the second value.Type: ApplicationFiled: October 24, 2019Publication date: September 10, 2020Inventors: Melin Dadual, Vivek Joy Kozhikkottu, Shankar Ganesh Ramasubramanian
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Publication number: 20200210284Abstract: Systems and methods related to data encoders that can perform error detection or correction. The encoders and decoders may minimize the addition of errors due to aliasing in error correction codes by implementing operators associated with reduced aliasing parity generating or reduced aliasing error checking matrices.Type: ApplicationFiled: December 28, 2018Publication date: July 2, 2020Inventors: Dinesh Somasekhar, Wei Wu, Shankar Ganesh Ramasubramanian, Vivek Kozhikkottu, Melin Dadual
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Publication number: 20200019513Abstract: Techniques for setting a 2-level auto-close timer to access a memory device include examples of setting first and second time values for the 2-level auto-close timer to cause accessed rows to auto-close following a cache line access to a row of a bank of memory devices. For these examples, the cache line access is responsive to a multi-channel address interleaving policy that causes either successive or non-successive cache line accesses to the bank of memory devices.Type: ApplicationFiled: September 26, 2019Publication date: January 16, 2020Inventors: Vivek KOZHIKKOTTU, Suresh CHITTOR, Esha CHOUKSE, Shankar Ganesh RAMASUBRAMANIAN
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Publication number: 20190280813Abstract: Embodiments may relate to a processor to an electronic device that includes an error correction code (ECC) encoder that is to perform ECC encoding on aa data message to generate an ECC encoded data message. The electronic device may further include a data bus inversion (DBI) encoder communicatively coupled with the ECC encoder, wherein the DBI encoder is to perform DBI encoding on the ECC encoded data message to generate a DBI encoded data message. Other embodiments may be described or claimed.Type: ApplicationFiled: May 23, 2019Publication date: September 12, 2019Applicant: Intel CorporationInventors: Vivek Joy Kozhikkottu, Shankar Ganesh Ramasubramanian, Dinesh Somasekhar, Melin Dadual
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Publication number: 20180285304Abstract: In accordance with embodiments disclosed herein, there is provided systems and methods for low latency statistical data bus inversion (DBI) for energy reduction. A transmitting component includes a transmitter and a statistical DBI circuit. The statistical DBI circuit is to receive current data to be transmitted on a data bus and is to store previous data transmitted on the data bus. The statistical DBI circuit includes inverting logic to invert bits of the current data before transmission in response to a control signal. The statistical DBI circuit includes adjacent pattern prediction logic to receive a difference vector including a comparison of the previous data and the current data, determine whether the difference vector includes a pattern predicting transmission of the current data with toggle is more efficient than without toggle, and output the control signal in the first state indicating the pattern was detected.Type: ApplicationFiled: March 31, 2017Publication date: October 4, 2018Inventors: Vivek Kozhikkottu, Shankar Ganesh Ramasubramanian, Kon-Woo Kwon, Dinesh Somasekhar
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Publication number: 20180188976Abstract: Devices, systems, and methods for increasing the size of a read pending queue (RPQ) in a memory controller are described. An example of increasing the RPQ size can include receiving, at a memory controller, a read request for data in a memory having a physical address identification (ID) including row and column ID, performing a lookup of the RPQ for an entry having a pending read transaction with a physical address ID having the same row ID as the incoming read request, and, if the RPQ lookup returns a hit, appending the incoming read request's column ID to the physical address ID of the pending read transaction to form an appended read transaction. The appending read transaction can then be queued and processed sequentially, while occupying a single RPQ entry.Type: ApplicationFiled: December 30, 2016Publication date: July 5, 2018Applicant: Intel CorporationInventors: Gunjae Koo, Vivek Kozhikkottu, Shankar Ganesh Ramasubramanian, Christopher B. Wilkerson