Patents by Inventor Shankar Muthukrisnan

Shankar Muthukrisnan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for fabricating an integrated gate dielectric layer for field effect transistors
    Patent number: 7601648
    Abstract: Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 ? utilized as a gate dielectric layer in a gate structure.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: October 13, 2009
    Assignee: Applied Materials, Inc.
    Inventors: Thai Cheng Chua, Shankar Muthukrisnan, Johanes Swenberg, Shreyas Kher, Chikuang Charles Wang, Giuseppina Conti, Yuri Uritsky
  • Method for fabricating an integrated gate dielectric layer for field effect transistors
    Publication number: 20080026553
    Abstract: Methods for forming a integrated gate dielectric layer on a substrate are provided. In one embodiment, the method includes forming a silicon oxide layer on a substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate. In another embodiment, the method includes precleaning a substrate, forming a silicon oxide layer on the substrate, plasma treating the silicon oxide layer, depositing a silicon nitride layer on the silicon oxide layer by an ALD process, and thermal annealing the substrate, wherein the formed silicon oxide layer and the silicon nitride layer has a total thickness less than 30 ? utilized as a gate dielectric layer in a gate structure.
    Type: Application
    Filed: July 31, 2006
    Publication date: January 31, 2008
    Inventors: Thai Cheng Chua, Shankar Muthukrisnan, Johanes Swenberg, Shreyas Kher, Chikuang Charles Wang, Giuseppina Conti, Yuri Uritsky