Patents by Inventor Shankar Regunathan

Shankar Regunathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080037657
    Abstract: Techniques and tools for performing fading compensation in video processing applications are described. For example, during encoding, a video encoder performs fading compensation using fading parameters comprising a scaling parameter and a shifting parameter on one or more reference images. During decoding, a video decoder performs corresponding fading compensation on the one or more reference images.
    Type: Application
    Filed: August 14, 2007
    Publication date: February 14, 2008
    Applicant: Microsoft Corporation
    Inventors: Sridhar Srinivasan, Shankar Regunathan
  • Publication number: 20070237226
    Abstract: Techniques and tools for switching distortion metrics during motion estimation are described. For example, a video encoder determines a distortion metric selection criterion for motion estimation. The criterion can be based on initial results of the motion estimation. To evaluate the criterion, the encoder can compare the criterion to a threshold that depends on a current quantization parameter. The encoder selects between multiple available distortion metrics, which can include a sample-domain distortion metric (e.g., SAD) and a transform-domain distortion metric (e.g., SAHD). The encoder uses the selected distortion metric in the motion estimation. Selectively switching between SAD and SAHD provides rate-distortion performance superior to using only SAD or only SAHD. Moreover, due to the lower complexity of SAD, the computational complexity of motion estimation with SAD-SAHD switching is typically less than motion estimation that always uses SAHD.
    Type: Application
    Filed: April 7, 2006
    Publication date: October 11, 2007
    Applicant: Microsoft Corporation
    Inventors: Shankar Regunathan, Chih-Lung Lin, Thomas Holcomb
  • Publication number: 20070237236
    Abstract: Techniques and tools are described for compensating for rounding when estimating sample-domain distortion in the transform domain. For example, a video encoder estimates pixel-domain distortion in the transform domain for a block of transform coefficients after compensating for rounding in the DC coefficient of the block. In this way, the video encoder improves the accuracy of pixel-domain distortion estimation but retains the computational advantages of performing the estimation in the transform domain. Rounding compensation includes, for example, looking up an index (from a de-quantized transform coefficient) in a rounding offset table to determine a rounding offset, then adjusting the coefficient by the offset. Other techniques and tools described herein are directed to creating rounding offset tables and encoders that make encoding decisions after considering rounding effects that occur after an inverse frequency transform on de-quantized transform coefficient values.
    Type: Application
    Filed: April 7, 2006
    Publication date: October 11, 2007
    Applicant: Microsoft Corporation
    Inventors: Cheng Chang, Chih-Lung Lin, Shankar Regunathan
  • Patent number: 7277486
    Abstract: Techniques and tools for performing fading compensation in video processing applications are described. For example, during encoding, a video encoder performs fading compensation using fading parameters comprising a scaling parameter and a shifting parameter on one or more reference images. During decoding, a video decoder performs corresponding fading compensation on the one or more reference images.
    Type: Grant
    Filed: March 3, 2003
    Date of Patent: October 2, 2007
    Assignee: Microsoft Corporation
    Inventors: Sridhar Srinivasan, Shankar Regunathan
  • Patent number: 7242713
    Abstract: A set of one and two-dimensional transforms is constructed subject to certain range limited constraints to provide a computationally efficient transform implementation, such as for use in image and video coding. The constraints can include that the transform has a scaled integer implementation, provides perfect or near perfect reconstruction, has a DCT-like basis, is limited to coefficient within a range for representation in n-bits (e.g., n is 16 bits), has basis functions that are close in norm, and provides sufficient headroom for overflow of the range. A set of transforms is constructed with this procedure having an implementation within a 16-bit integer range for efficient computation using integer matrix multiplication operations.
    Type: Grant
    Filed: February 28, 2003
    Date of Patent: July 10, 2007
    Assignee: Microsoft Corporation
    Inventors: Sridhar Srinivasan, Shankar Regunathan
  • Publication number: 20070036222
    Abstract: A block transform-based digital media codec efficiently compresses digital media data using block patterns representing whether a block's coefficients are zero- valued, such that their explicit encoding is skipped. Because the block patterns can have widely varying probability distributions, the codec adaptively chooses a prediction mode for modifying the block patterns (e.g., based on spatial prediction, or inverting) to enhance their compression using entropy coding techniques. Further, with high spatial correlation of block patterns, the codec encodes a meta block pattern for a region indicating whether all block patterns of the region represent zero-valued coefficient blocks. In such cases, the codec can then also omit explicitly encoding the block patterns in those regions.
    Type: Application
    Filed: August 12, 2005
    Publication date: February 15, 2007
    Applicant: Microsoft Corporation
    Inventors: Sridhar Srinivasan, Chengjie Tu, Shankar Regunathan
  • Patent number: 7162093
    Abstract: A video encoder/decoder utilizes a bistream syntax that provides an independently decodable, partial picture unit, which may be in the form of a unit containing one or more contiguous rows of macroblocks (called a slice). This slice layer provides a flexible combination of error-resilience and compression efficiency. The slice layer encodes an efficient addressing mechanism (e.g., a syntax element specifying a beginning macroblock row of the slice layer), as well as an efficient mechanism to optionally retransmit picture header information. The slice layer provides decoding and reconstruction independence by disabling all forms of prediction, overlap and loop-filtering across slice-boundaries. This permits a slice coded in intra-mode to be reconstructed error-free, irrespective of errors in other regions of the picture.
    Type: Grant
    Filed: September 3, 2004
    Date of Patent: January 9, 2007
    Assignee: Microsoft Corporation
    Inventors: Shankar Regunathan, Pohsiang Hsu, Ce Wang, Chih-Lung Lin, Jie Liang, Sridhar Srinivasan
  • Publication number: 20060146830
    Abstract: Various new and non-obvious apparatus and methods for using frame caching to improve packet loss recovery are disclosed. One of the disclosed embodiments is a method for using periodical and synchronized frame caching within an encoder and its corresponding decoder. When the decoder discovers packet loss, it informs the encoder which then generates a frame based on one of the shared frames stored at both the encoder and the decoder. When the decoder receives this generated frame it can decode it using its locally cached frame.
    Type: Application
    Filed: December 30, 2004
    Publication date: July 6, 2006
    Applicant: Microsoft Corporation
    Inventors: Chih-Lung Lin, Minghui Xia, Pohsiang Hsu, Shankar Regunathan, Thomas Holcomb
  • Publication number: 20050152457
    Abstract: A video codec efficiently signals that a frame is identical to its reference frame, such that separate coding of its picture content is skipped. Information that a frame is skipped is represented jointly in a coding table of a frame coding type element for bit rate efficiency in signaling. Further, the video codec signals the picture type (e.g., progressive or interlaced) of skipped frames, which permits different repeat padding methods to be applied according to the picture type.
    Type: Application
    Filed: November 12, 2004
    Publication date: July 14, 2005
    Applicant: Microsoft Corporation
    Inventors: Shankar Regunathan, Chih-Lung Lin, Thomas Holcomb, Jie Liang, Ming-Chieh Lee, Pohsiang Hsu
  • Publication number: 20050152448
    Abstract: A video decoder receives an entry point key frame comprising first and second interlaced video fields and decodes a first syntax element comprising information (e.g., frame coding mode) for the entry point key frame at a first syntax level (e.g., frame level) in a bitstream. The first interlaced video field is a predicted field, and the second interlaced video field is an intra-coded field. The information for the entry point key frame can be a frame coding mode (e.g., field interlace) for the entry point key frame. The decoder can decode a second syntax element at the first syntax level comprising second information (e.g., field type for each of the first and second interlaced video fields) for the entry point key frame.
    Type: Application
    Filed: November 15, 2004
    Publication date: July 14, 2005
    Applicant: Microsoft Corporation
    Inventors: Regis Crinon, Thomas Holcomb, Shankar Regunathan, Sridhar Srinivasan
  • Publication number: 20050123274
    Abstract: A decoder receives an entry point header comprising plural control parameters for an entry point segment corresponding to the entry point header. The entry point header is in an entry point layer of a bitstream comprising plural layers. The decoder decodes the entry point header. The plural control parameters can include various combinations of control parameters such as a pan scan on/off parameter, a reference frame distance on/off parameter, a loop filtering on/off parameter, a fast chroma motion compensation on/off parameter, an extended range motion vector on/off parameter, a variable sized transform on/off parameter, an overlapped transform on/off parameter, a quantization decision parameter, and an extended differential motion vector coding on/off parameter, a broken link parameter, a closed entry parameter, one or more coded picture size parameters, one or more range mapping parameters, a hypothetical reference decoder buffer parameter, and/or other parameter(s).
    Type: Application
    Filed: November 15, 2004
    Publication date: June 9, 2005
    Applicant: Microsoft Corporation
    Inventors: Regis Crinon, Chih-Lung Lin, Jie Liang, Shankar Regunathan, Shuo-Jen Wu, Timothy Onders, Thomas Holcomb
  • Publication number: 20050105883
    Abstract: Techniques and tools for coding/decoding of digital video, and in particular, for determining, signaling and detecting entry points in video streams are described. Techniques and tools described herein are used to embed entry point indicator information in the bitstream that receivers, editing systems, insertion systems, and other systems can use to detect valid entry points in compressed video.
    Type: Application
    Filed: June 30, 2004
    Publication date: May 19, 2005
    Applicant: Microsoft Corporation
    Inventors: Thomas Holcomb, Regis Crinon, Timothy Onders, Sridhar Srinivasan, Shankar Regunathan
  • Publication number: 20050099869
    Abstract: A decoder receives a field start code for an entry point key frame. The field start code indicates a second coded interlaced video field in the entry point key frame following a first coded interlaced video field in the entry point key frame and indicates a point to begin decoding of the second coded interlaced video field. The first coded interlaced video field is a predicted field, and the second coded interlaced video field is an intra-coded field. The decoder decodes the second field without decoding the first field. The field start code can be followed by a field header. The decoder can receive a frame header for the entry point key frame. The frame header may comprise a syntax element indicating a frame coding mode for the entry point key frame and/or a syntax element indicating field types for the first and second coded interlaced video fields.
    Type: Application
    Filed: November 15, 2004
    Publication date: May 12, 2005
    Applicant: Microsoft Corporation
    Inventors: Regis Crinon, Thomas Holcomb, Shankar Regunathan, Sridhar Srinivasan
  • Publication number: 20050083218
    Abstract: A decoder processes a first bitstream element (e.g., a pull-down flag) in a first syntax layer (e.g., sequence layer or entry point layer) above frame layer in a bitstream for a video sequence, the bitstream comprising encoded source video having a source type (e.g., progressive or interlace). The decoder processes frame data in a second syntax layer (e.g., frame layer) of the bitstream for a frame (such as an interlaced frame or progressive frame, depending on source type, or a skipped frame) in the video sequence. The first bitstream element indicates whether a repeat-picture element (e.g., a repeat-frame element or a repeat field-element) is present or absent in the frame data in the second syntax layer.
    Type: Application
    Filed: September 4, 2004
    Publication date: April 21, 2005
    Applicant: Microsoft Corporation
    Inventors: Shankar Regunathan, Chih-Lung Lin, Thomas Holcomb, Kunal Mukerjee, Pohsiang Hsu
  • Publication number: 20050074061
    Abstract: Techniques and tools are described for signaling hypothetical reference decoder parameters for video bitstreams, including signaling of buffer fullness. For example, a buffer size syntax element indicates a decoder buffer size, and a buffer fullness syntax element indicates a buffer fullness as a fraction of the decoder buffer size. As another example, buffer fullness is signaled in one or more entry point headers and other hypothetical reference decoder parameters are signaled in a sequence header.
    Type: Application
    Filed: September 2, 2004
    Publication date: April 7, 2005
    Applicant: Microsoft Corporation
    Inventors: Jordi Ribas-Corbera, Sridhar Srinivasan, Shankar Regunathan, Regis Crinon
  • Publication number: 20050063471
    Abstract: Techniques and tools are described for flexible range reduction of samples of video. For example, an encoder signals a first set of one or more syntax elements for range reduction of luma samples and signals a second set of one or more syntax elements for range reduction of chroma samples. The encoder selectively scales down the luma samples and chroma samples in a manner consistent with the first syntax element(s) and second syntax element(s), respectively. Or, an encoder signals range reduction syntax element(s) in an entry point header for an entry point segment, where the syntax element(s) apply to pictures in the entry point segment. If range reduction is used for the pictures, the encoder scales down samples of the pictures. Otherwise, the encoder skips the scaling down. A decoder performs corresponding parsing and scaling up operations.
    Type: Application
    Filed: November 15, 2004
    Publication date: March 24, 2005
    Applicant: Microsoft Corporation
    Inventors: Shankar Regunathan, Sridhar Srinivasan, Jie Liang, Chih-Lung Lin, Minghui Xia
  • Publication number: 20050052294
    Abstract: Entropy coding and decoding techniques are described, which may be implemented separately or in combination. For example, a video encoder uses two-layer run level coding to reduce bitrate for frequency transform coefficients in a quick and efficient manner, and a video decoder uses corresponding two-layer run level decoding. This two-layer coding/decoding can be generalized to more than two layers of run level coding/decoding. The video encoder and decoder exploit common patterns in run level information to reduce code table size and create opportunities for early termination of decoding. Using zoned Huffman code tables helps limit overall table size while still providing a level of adaptivity in encoding and decoding. Using embedded Huffman code tables allows the encoder and decoder to reuse codes for 8×8, 8×4, 4×8, and 4×4 blocks.
    Type: Application
    Filed: April 15, 2004
    Publication date: March 10, 2005
    Inventors: Jie Liang, Chih-Lung Lin, Shankar Regunathan, Sridhar Srinivasan
  • Publication number: 20050053158
    Abstract: A video encoder/decoder utilizes a bistream syntax that provides an independently decodable, partial picture unit, which may be in the form of a unit containing one or more contiguous rows of macroblocks (called a slice). This slice layer provides a flexible combination of error-resilience and compression efficiency. The slice layer encodes an efficient addressing mechanism (e.g., a syntax element specifying a beginning macroblock row of the slice layer), as well as an efficient mechanism to optionally retransmit picture header information. The slice layer provides decoding and reconstruction independence by disabling all forms of prediction, overlap and loop-filtering across slice-boundaries. This permits a slice coded in intra-mode to be reconstructed error-free, irrespective of errors in other regions of the picture.
    Type: Application
    Filed: September 3, 2004
    Publication date: March 10, 2005
    Applicant: Microsoft Corporation
    Inventors: Shankar Regunathan, Pohsiang Hsu, Ce Wang, Chih-Lung Lin, Jie Liang, Sridhar Srinivasan
  • Publication number: 20050053155
    Abstract: Techniques and tools for intensity compensation for interlaced forward-predicted fields are described. For example, a video decoder receives and decodes a variable length code that indicates which of two reference fields for an interlaced forward-predicted field use intensity compensation (e.g., both, only the first, or only the second). The decoder performs intensity compensation on each of the two reference fields that uses intensity compensation. A video encoder performs corresponding intensity estimation/compensation and signaling.
    Type: Application
    Filed: September 2, 2004
    Publication date: March 10, 2005
    Applicant: Microsoft Corporation
    Inventors: Thomas Holcomb, Sridhar Srinivasan, Shankar Regunathan
  • Publication number: 20050041738
    Abstract: Described tools and techniques relate to signaling for DC coefficients at small quantization step sizes. The techniques and tools can be used in combination or independently. For example, a tool such as a video encoder or decoder processes a VLC that indicates a DC differential for a DC coefficient, a FLC that indicates a value refinement for the DC differential, and a third code that indicates the sign for the DC differential. Even with the small quantization step sizes, the tool uses a VLC table with DC differentials for DC coefficients above the small quantization step sizes. The FLCs for DC differentials have lengths that vary depending on quantization step size.
    Type: Application
    Filed: July 17, 2004
    Publication date: February 24, 2005
    Applicant: Microsoft Corporation
    Inventors: Chih-Lung Lin, Shankar Regunathan, Sridhar Srinivasan