Patents by Inventor Shankar Sinha
Shankar Sinha has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8482963Abstract: Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.Type: GrantFiled: December 2, 2009Date of Patent: July 9, 2013Assignee: Altera CorporationInventors: Jun Liu, Yanzhong Xu, Shankar Sinha, Shih-Lin S. Lee, Jeffrey Xiaoqi Tung, Albert Ratnakumar, Qi Xiang, Irfan Rahim, Andy L. Lee, Jeffrey T. Watt, Srinivas Perisetty
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Patent number: 8409952Abstract: A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.Type: GrantFiled: April 14, 2008Date of Patent: April 2, 2013Assignee: Spansion LLCInventors: Suketu Arun Parikh, Olov B. Karlsson, Yun Sun, Shankar Sinha, Timothy Thurgate
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Publication number: 20120311401Abstract: Integrated circuits with multiport memory elements may be provided. A multiport memory element may include a latching circuit, a first set of address transistors, and a second set of address transistors. The latching circuit may include cross-coupled inverters, each of which includes a pull-up transistor and a pull-down transistor. The first set of address transistors may couple the latching circuit to a write port, whereas the second set of address transistors may couple the latching circuit to a read port. The pull-down transistors and the second set of address transistors may have body bias terminals that are controlled by a control signal. During data loading operations, the control signal may be temporarily elevated to weaken the pull-down transistors and the second set of address transistors to improve the write margin of the multiport memory element.Type: ApplicationFiled: May 31, 2011Publication date: December 6, 2012Inventors: Shih-Lin S. Lee, Peter J. McElheny, Preminder Singh, Shankar Sinha
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Patent number: 8218353Abstract: Integrated circuits with memory elements are provided. The memory elements may be arranged in a memory block. The memory block may include cross-coupled inverters that store data. The stored data may be used to program pass transistors. Transistors in the memory block may be stressed. Depending on the type of stress-inducing layer used, a tensile stress or a compressive stress may be built in into the transistors. Stressed transistors may help improve the routing speed of the memory block. Stressed transistors may be implemented using dual gate-oxide process.Type: GrantFiled: September 16, 2009Date of Patent: July 10, 2012Assignee: Altera CorporationInventors: Jun Liu, Shankar Sinha, Qi Xiang, Yow-Juang Liu
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Patent number: 8148770Abstract: A memory device includes a number of memory cells and a bit line structure coupled to a group of the memory cells. The bit line structure includes an upper portion having a first width, and a lower portion having a second width, where the first width is less than the second width.Type: GrantFiled: June 24, 2005Date of Patent: April 3, 2012Assignee: Spansion LLCInventors: Shankar Sinha, Timothy Thurgate
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Patent number: 7888218Abstract: The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a first polysilicon layer and defining a first bitline opening there between, forming first polysilicon layer features over the charge trapping dielectric layer, depositing a layer of second spacer material over the charge trapping dielectric and the first polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the first polysilicon layer features to define a second bitline opening between the adjacent memory cells, performing a bitline implant, or pocket implants, or both into the bitline opening to establish buried bitlines within the substrate having respective bitline widths that are narrower than the respective widths of the first bitline openings, removing the sidewall spacers, and performing back endType: GrantFiled: March 16, 2007Date of Patent: February 15, 2011Assignee: Spansion LLCInventors: Zhizheng Liu, Shankar Sinha, Timothy Thurgate, Ming-Sang Kwan
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Patent number: 7678674Abstract: A method of forming implants for a memory cell includes forming an oxide-nitride-oxide (ONO) stack over a substrate and implanting first impurities in the substrate adjacent each side of the ONO stack using a first implantation energy and a first tilt angle to produce first pocket implants. The method further includes implanting second impurities in the substrate adjacent each side of the ONO stack using a second implantation energy and a second tilt angle to produce second pocket implants, where the second implantation energy is substantially larger than the first implantation energy and where the second tilt angle is substantially larger than the first tilt angle.Type: GrantFiled: August 26, 2005Date of Patent: March 16, 2010Assignee: Spansion LLCInventors: Shankar Sinha, Ashot Melik-Martirosian, Ihsan Djomehri
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Publication number: 20090256242Abstract: A method of forming an electronic device including forming a first trench in a workpiece including a substrate, the first trench having side walls and a bottom surface extending for a width between the side walls and forming a charge-storage layer along the side walls and bottom surface of the first trench. The method further includes implanting ions within the substrate underlying the bottom surface of the first trench to form an implant region and annealing the implant region, wherein after annealing, the implant region extends the width of the bottom surface and along a portion of the side walls.Type: ApplicationFiled: April 14, 2008Publication date: October 15, 2009Applicant: SPANSION LLCInventors: Suketu Arun Parikh, Olov B. Karlsson, Yu Sun, Shankar Sinha, Timothy Thurgate
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Patent number: 7561457Abstract: A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory array and with substantially the same channel length.Type: GrantFiled: August 18, 2006Date of Patent: July 14, 2009Assignee: Spansion LLCInventors: Mark Randolph, Zhizheng Liu, Ashot Melik-Martirosian, Yi He, Shankar Sinha
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Patent number: 7476604Abstract: A method of forming a contact through a material includes forming a via through a dielectric material and cleaning the via using a dilute hydrofluoric (DHF) acid solution. The method further includes depositing a barrier layer within the via and depositing metal adjacent the barrier layer.Type: GrantFiled: May 13, 2005Date of Patent: January 13, 2009Assignees: Advanced Micro Devices, Inc., Spansion LLCInventors: Ning Cheng, Minh Van Ngo, Jinsong Yin, Paul Raymond Besser, Connie Pin-chin Wang, Russell Rosaire Austin Callahan, Jeffrey Shields, Shankar Sinha, Jeff P. Erhardt, Jeremy Chi-Hung Chou
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Publication number: 20080157199Abstract: In patterning a transistor, some of a layer of gate dielectric material is allowed to remain over a semiconductor substrate upon which the transistor is formed. This remaining dielectric material retards the implantation of dopants into the underlying substrate, effectively lengthening a channel region of the transistor. This mitigates unwanted short channel effects, such as leakage currents, for example, and thus mitigates yield loss by establishing a transistor that performs in a more predictable or otherwise desirable manner.Type: ApplicationFiled: March 16, 2007Publication date: July 3, 2008Inventors: Vidyut Gopal, Shankar Sinha, Jean Yee-Mei Yang, Phillip L. Jones
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Publication number: 20080153223Abstract: The present invention pertains to a system method of forming at least a portion of a dual bit memory core array upon a semiconductor substrate, the method comprising forming adjacent first memory cell process assemblies; comprising a charge trapping dielectric, a first polysilicon layer and defining a first bitline opening there between, forming first polysilicon layer features over the charge trapping dielectric layer, depositing a layer of second spacer material over the charge trapping dielectric and the first polysilicon layer features, forming a sidewall spacer adjacent to the charge trapping dielectric and the first polysilicon layer features to define a second bitline opening between the adjacent memory cells, performing a bitline implant, or pocket implants, or both into the bitline opening to establish buried bitlines within the substrate having respective bitline widths that are narrower than the respective widths of the first bitline openings, removing the sidewall spacers, and performing back endType: ApplicationFiled: March 16, 2007Publication date: June 26, 2008Inventors: Zhizheng Liu, Shankar Sinha, Timothy Thurgate, Ming-Sang Kwan
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Publication number: 20080135902Abstract: One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.Type: ApplicationFiled: December 6, 2006Publication date: June 12, 2008Inventors: Shankar Sinha, Yi He, Zhizheng Liu, Ming-Sang Kwan
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Publication number: 20080123384Abstract: A semiconductor device includes a core memory array and a periphery area. The core memory array area includes a group of memory cells. The periphery area includes a group of select transistors. The select transistors are formed at substantially the same pitch as the memory cells in the core memory array and with substantially the same channel length.Type: ApplicationFiled: August 18, 2006Publication date: May 29, 2008Applicant: SPANSION LLCInventors: Mark RANDOLPH, Zhizheng LIU, Ashot MELIK-MARTIROSIAN, Yi HE, Shankar SINHA
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Patent number: 7269067Abstract: A method of programming a memory cell in a non-volatile memory device includes applying a first voltage to a control gate associated with the memory cell and applying a second voltage to a drain region associated with the memory cell. The method also includes applying a positive bias to a source region associated with the memory cell and/or applying a negative bias to a substrate region associated with the memory cell.Type: GrantFiled: July 6, 2005Date of Patent: September 11, 2007Assignee: Spansion LLCInventors: Shankar Sinha, Zhizheng Liu, Yi He
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Publication number: 20070008782Abstract: A method of programming a memory cell in a non-volatile memory device includes applying a first voltage to a control gate associated with the memory cell and applying a second voltage to a drain region associated with the memory cell. The method also includes applying a positive bias to a source region associated with the memory cell and/or applying a negative bias to a substrate region associated with the memory cell.Type: ApplicationFiled: July 6, 2005Publication date: January 11, 2007Inventors: Shankar Sinha, Zhizheng Liu, Yi He
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Patent number: 6642119Abstract: The present invention relates to a method of forming a transistor and a transistor structure. The invention comprises forming the transistor using a double silicide process which reduces resistance and reduces the floating-body-effect when employed in conjunction with SOI type device architecture.Type: GrantFiled: August 8, 2002Date of Patent: November 4, 2003Assignee: Advanced Micro Devices, Inc.Inventors: Mario M. Pelella, Shankar Sinha, Simon S. Chan