Patents by Inventor ShankarGanesh Kandasamy

ShankarGanesh Kandasamy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250190225
    Abstract: Aspects disclosed in the detailed description include a processing unit for dynamically reconfiguring micro-architectural features of the processing unit in response to a workload being processed on the processing unit and a processing unit control unit configured to receive a plurality of signals from the processing unit. The plurality of signals are indicia of the workload being processed on the processing unit. In response, the processing unit control unit determines whether performance, power consumption, or both, of the processing unit may be improved by modifying a micro-architectural feature. In response to determining that performance or power consumption of the processing unit may be improved by modifying micro-architectural features, the processing unit control unit triggers the processing unit to modify one or more of its micro-architectural features. The processing unit, in response to being triggered by the processing unit control unit, modifies one or more of its micro-architectural features.
    Type: Application
    Filed: December 8, 2023
    Publication date: June 12, 2025
    Inventors: Monobrata Debnath, Ajaykumar Shankargouda Patil, Anantha Ramaiah Idapalapati, Shankarganesh Kandasamy, Azzedine Adam Touzni
  • Patent number: 10489300
    Abstract: Certain aspects of the present disclosure provide techniques for increasing processor caching efficiency by cache data pattern optimization. One embodiment includes a method for managing data in a cache, including: receiving data to be cached at the cache; determining that the data to be cached matches a predefined data pattern; and updating a tag RAM associated with the cache with a pattern tag comprising tag bits and pattern bits, wherein the pattern bits match the predefined data pattern.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: November 26, 2019
    Assignee: Qualcomm Incorporated
    Inventors: Sankaran Nampoothiri, Subodh Singh, ShankarGanesh Kandasamy, Avinash Philip