Abstract: Memory system for internally rearranging fields in database records. The memory is separated into modules, each module separately addressable. Each memory module is addressed by selectively modifying a supplied address, for example by the output from exclusive-OR gates, having inputs from the address supplied to the memory system and another inputs from address modification registers. The address modification registers are selectively set by the external utilization device to permit reading different rows in the memory modules, The data output columns from the memory modules can be rearranged using selector devices such as demultiplexors. Data can be masked by precluding certain selector control signals.

Abstract: A memory fault mapping apparatus detects faults generated in a memory array during on-line operation. As the memory array is randomly accessed, single bit error are detected, corrected, and mapped into an error memory. The errors may be mapped in an error memory having a memory location for each memory of the memory array or alternatively, by grouping memories together and when the errors generated by any one group exceeds a predetermined threshold of errors, testing only the memories in that group off-line. By grouping the memories a substantial reduction in the amount of error memory required can be achieved. A SEC/DED syndrome generator detects single and double bit errors, correcting the single bit errors while providing an indication of which memory generated the error. An error memory stores error counts for the memory array, each error count indicating the number of errors for a specific memory or a group of memories.

Abstract: An array substitution scheme is used to substitute a spare chip for a faulty chip when a UE condition results from an alignment of two errors in bit positions accessed through the same decoder while the bit permutation apparatus is used to misalign fault bits when they occur in bit positions accessed through different decoders.

Abstract: Spare chips are employed together with a replacement algorithm to replace chips in memory array when failure is generally more extensive then unrelated cell fails in the memory chips. That is, substitution will be made if an error condition is a result of the failure of a whole chip (chip-kill), a segment of a chip (island-kill), a column of bits of a chip or a row of bits of a chip but will not be performed when it is due to a single failed cell. The replacement of a chip with a chip-kill or with an island-kill is done on the fly and involves only a row of the memory chips or elements leaving other elements of the memory unaffected by the replacement.

Abstract: This permutation circuit can be considered to be a multi-bit adder without a carry. In one embodiment it takes the form of m address bits being fed to m+y 2-way exclusive OR gates with m+y permutation bits to generate m+y input bits accessing a decoder with 2.sup.m output positions. In another embodiment the decoder takes the form an m bit adder with which adds m address bits to m permutation bits to generate m bit actual address. Multiple decoders of both types may be joined together in various combinations to generate higher order addresses. Also, k full-adder of less than m bits can also be used in similar fashion as m+y Exor gates to provide shift rotate capability within a desired block of 2.sup.y rows.

Abstract: Swapping of bits between different words of a memory is accomplished by reference to data on bad bits in the memory. This data controls address inputs to each bit in a memory word so that any word with multiple uncorrectable errors is changed to a correctable data word by placing one or more of the bad bits in the word into another word of the memory. The data is used in maintaining a list of preferred word address locations for bad bits. These preferred word locations are word addresses which contain less than a threshold level of faulty bit positions. As each faulty bit is permuted into one of these preferred word addresses, the list is updated to account for the new location of the permuted bit. Before being permuted, the actual physical memory address of a fault is used in making up the list. After permutation, the logical address of the faulty bit is used in changing the list.

Abstract: An improved system for adding two numbers together. The numbers may be expressed either in binary form or in binary coded decimal form (wherein each decimal digit is represented by its equivalent four binary bits). By taking advantage of "don't care" decimal input conditions, a minimal implementation of a carry look-ahead adder which can operate upon both types of numbers is obtained.