Abstract: A circuit includes a gain stage, first and second amplifiers, and a comparison circuit. The gain stage has an input and an output. The first amplifier has an input and an output. The input of the first amplifier is coupled to the input of the gain stage. The second amplifier has an input and an output. The input of the second amplifier is coupled to the output of the gain stage. The comparison circuit is coupled to the outputs of the first and second amplifiers. The comparison circuit is configured to compare signals on the outputs of the first and second amplifiers and to generate a fault flag signal responsive to the output signal from the first amplifier being different than the output signal from the second amplifier.

Abstract: An automatic gain control circuit includes a linear-to-log conversion circuit, a current amplifier circuit, and an amplitude sense circuit. The current amplifier circuit includes a current input terminal coupled to an output terminal of the linear-to-log conversion circuit. The amplitude sense circuit includes an input terminal coupled to an output terminal of the current amplifier circuit, and an output terminal coupled to a gain control input terminal of the current amplifier circuit.

Abstract: A circuit includes a gain stage, first and second amplifiers, and a comparison circuit. The gain stage has an input and an output. The first amplifier has an input and an output. The input of the first amplifier is coupled to the input of the gain stage. The second amplifier has an input and an output. The input of the second amplifier is coupled to the output of the gain stage. The comparison circuit is coupled to the outputs of the first and second amplifiers. The comparison circuit is configured to compare signals on the outputs of the first and second amplifiers and to generate a fault flag signal responsive to the output signal from the first amplifier being different than the output signal from the second amplifier.

Abstract: A system includes a sensor integrated circuit (IC), including a driver adapted to be coupled to an oscillator, the driver including first and second transistors. The sensor IC includes an amplitude control amplifier coupled to the first transistor. The sensor IC also includes a common mode control amplifier coupled to the second transistor. The sensor IC includes a handover control circuit coupled to the amplitude control amplifier and configured to hand off an operation from the sensor IC to a different sensor IC, the handover control circuit including a resistor network coupled to a switch network.

Abstract: A circuit includes a gain stage, first and second amplifiers, and a comparison circuit. The gain stage has an input and an output. The first amplifier has an input and an output. The input of the first amplifier is coupled to the input of the gain stage. The second amplifier has an input and an output. The input of the second amplifier is coupled to the output of the gain stage. The comparison circuit is coupled to the outputs of the first and second amplifiers. The comparison circuit is configured to compare signals on the outputs of the first and second amplifiers and to generate a fault flag signal responsive to the output signal from the first amplifier being different than the output signal from the second amplifier.

Abstract: A circuit includes a bandpass filter and a self-tracking circuit. The bandpass filter has a first input node configured to receive an input square wave signal and an output node configured to provide an output sine wave signal. The bandpass filter includes a first binary-weighted programmable resistor array. The self-tracking circuit includes a second input node coupled to the output node. The self-tracking circuit includes a counter, and the counter includes an output node coupled to the first binary weighted programmable resistor array.

Abstract: An automatic gain control circuit includes a linear-to-log conversion circuit, a current amplifier circuit, and an amplitude sense circuit. The current amplifier circuit includes a current input terminal coupled to an output terminal of the linear-to-log conversion circuit. The amplitude sense circuit includes an input terminal coupled to an output terminal of the current amplifier circuit, and an output terminal coupled to a gain control input terminal of the current amplifier circuit.

Abstract: An angular resolver system includes, for example, an imbalance detector for detecting degraded resolver output signals. The imbalance detector includes a first and second power averaging circuits and a comparator circuit. The first power averaging circuit includes a first integrator for generating over a first time window a first average power signal in response to resolver sensor output signals. The second power averaging circuit includes a second integrator for generating over a second time window a second average power signal in response to the resolver sensor output signals, where the first time window is longer than the second time window. The comparator circuit compares the first average power signal and the second average power signal and generates a fault signal when the first average power signal and the second average power signal differ by a selected voltage threshold.

Abstract: A circuit includes a bandpass filter and a self-tracking circuit. The bandpass filter has a first input node configured to receive an input square wave signal and an output node configured to provide an output sine wave signal. The bandpass filter includes a first binary-weighted programmable resistor array. The self-tracking circuit includes a second input node coupled to the output node. The self-tracking circuit includes a counter, and the counter includes an output node coupled to the first binary weighted programmable resistor array.

Abstract: A protection device includes a dynamic gate bias circuit and an input pass switch. The dynamic gate bias circuit comprises an input pass switch configured to receive a first input and a first control signal; a voltage level shifter coupled to the input pass switch; a current mirror coupled to the voltage level shifter at a first node; a regulator coupled to the current mirror at a second node; and a transistor coupled to the first node, wherein the transistor is configured to receive a second control signal from the first node and to receive the first input.

Abstract: A circuit includes a bandpass filter and a self-tracking circuit. The bandpass filter has a first input node configured to receive an input square wave signal and an output node configured to provide an output sine wave signal. The bandpass filter includes a first binary-weighted programmable resistor array. The self-tracking circuit includes a second input node coupled to the output node. The self-tracking circuit includes a counter, and the counter includes an output node coupled to the first binary weighted programmable resistor array.

Abstract: A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.

Abstract: A protection device includes a dynamic gate bias circuit and an input pass switch. The dynamic gate bias circuit comprises an input pass switch configured to receive a first input and a first control signal; a voltage level shifter coupled to the input pass switch; a current mirror coupled to the voltage level shifter at a first node; a regulator coupled to the current mirror at a second node; and a transistor coupled to the first node, wherein the transistor is configured to receive a second control signal from the first node and to receive the first input.

Abstract: Methods, apparatus, systems and articles of manufacture to increase resolver-to-digital converter accuracy are disclosed.

Abstract: A voltage regulator and a gate control circuit for an aid transistor coupled to assist a pass element for the voltage regulator during line transients having a given slope are disclosed. The gate control circuit includes a first circuit coupled to receive an output voltage of the voltage regulator on a first node and to provide a gate control voltage that mirrors the output voltage on a second node. A low pass filter is coupled to receive the gate control voltage and to provide a filtered gate control voltage to the gate of the aid transistor.

Abstract: A current sink circuit coupled to pull down a gate control node (GCN) for an NMOS power FET that controls an actuator includes first and second NMOS transistors coupled in series between the GCN and a lower rail, where the first NMOS transistor has a gate and drain coupled together through a resistor. The current sink circuit also includes a control signal generation circuit (CSGC) and a negative voltage blocking circuit (NVBC). The CSGC is coupled to receive at least one voltage input and an ignition signal and to provide a first control signal and a second control signal. The NVBC is coupled to pass the first control signal from the control signal generation circuit to the gate of the first NMOS transistor and to block a negative voltage on the GCN from reaching the CSGC. The second control signal is coupled to the gate of the second NMOS transistor.

Abstract: A voltage regulator and a gate control circuit for an aid transistor coupled to assist a pass element for the voltage regulator during line transients having a given slope are disclosed. The gate control circuit includes a first circuit coupled to receive an output voltage of the voltage regulator on a first node and to provide a gate control voltage that mirrors the output voltage on a second node. A low pass filter is coupled to receive the gate control voltage and to provide a filtered gate control voltage to the gate of the aid transistor.

Abstract: An angular resolver system includes, for example, an imbalance detector for detecting degraded resolver output signals. The imbalance detector includes a first and second power averaging circuits and a comparator circuit. The first power averaging circuit includes a first integrator for generating over a first time window a first average power signal in response to resolver sensor output signals. The second power averaging circuit includes a second integrator for generating over a second time window a second average power signal in response to the resolver sensor output signals, where the first time window is longer than the second time window. The comparator circuit compares the first average power signal and the second average power signal and generates a fault signal when the first average power signal and the second average power signal differ by a selected voltage threshold.

Abstract: Methods, apparatus, systems and articles of manufacture to increase resolver-to-digital converter accuracy are disclosed.

Abstract: A circuit includes an input pin connected to an integrated circuit (IC) that receives an input voltage that is provided to a first voltage circuit within the IC. A pass device having a control input responds to a first control signal state and a second control signal state. The first control signal state turns the pass device off such that the input voltage is switched off to block the passing of the input voltage to a second voltage circuit within the IC. The second control signal state turns the pass device on such that the input voltage is switched through the pass device to the second voltage circuit in a voltage range that is compatible with an input operating voltage range of the second voltage circuit.