Abstract: The present invention provides an event edge synchronization system and a method of operating the same. In one embodiment, the event edge synchronization system includes: (1) a first clock zone device configured to generate an event signal based upon a first clock rate, (2) a second clock zone device configured to operate at a second clock rate, which is asynchronous with the first clock rate and (3) a synchronous notification subsystem configured to receive the event signal, synchronize the event signal to the second clock rate based upon an edge transition of the event signal and the second clock rate, and generate a synchronous notification signal therefrom.

Abstract: The present invention provides an event edge synchronization system and a method of operating the same. In one embodiment, the event edge synchronization system includes: (1) a first clock zone device configured to generate an event signal based upon a first clock rate, (2) a second clock zone device configured to operate at a second clock rate, which is asynchronous with the first clock rate and (3) a synchronous notification subsystem configured to receive the event signal, synchronize the event signal to the second clock rate based upon an edge transition of the event signal and the second clock rate, and generate a synchronous notification signal therefrom.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: For use with a fast pattern processor having an internal function bus, an external device transmission system, method for transmitting commands to an external device, and a fast pattern processor employing the system and method. In one embodiment, the external device transmission system includes a context memory subsystem that maintains a plurality of argument signature registers, each of the plurality of argument signature registers being associated with a corresponding context and containing a corresponding argument. The external device transmission system also includes a pattern processing engine that dynamically modifies an argument and generates a transmit command as a function of a context associated with the modified argument. The external device transmission system still further includes an output interface subsystem that receives the transmit command, and transmits the modified argument based upon the transmit command to an external device.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.

Abstract: For use with a fast pattern processor having an internal function bus, an external device transmission system, method for transmitting commands to an external device, and a fast pattern processor employing the system and method. In one embodiment, the external device transmission system includes a context memory subsystem that maintains a plurality of argument signature registers, each of the plurality of argument signature registers being associated with a corresponding context and containing a corresponding argument. The external device transmission system also includes a pattern processing engine that dynamically modifies an argument and generates a transmit command as a function of a context associated with the modified argument. The external device transmission system still further includes an output interface subsystem that receives the transmit command, and transmits the modified argument based upon the transmit command to an external device.

Abstract: A virtual reassembly system for use with a fast pattern processor and a method of operating the same. In one embodiment, the virtual reassembly system includes a first pass subsystem configured to convert a packet of a protocol data unit into at least one processing block, queue the at least one processing block based upon a header of the packet and determine if the packet is a last packet of the protocol data unit. The virtual reassembly system further includes a second pass subsystem configured to virtually reassemble the protocol data unit by retrieving the at least one processing block based upon the queue.