Patents by Inventor Shantanu Mishra

Shantanu Mishra has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • COMPILER-BASED GENERATION OF TRANSACTION ACCURATE MODELS FROM HIGH-LEVEL LANGUAGES
    Publication number: 20240012629
    Abstract: Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that specifies an assembly language version of the kernel as instrumented.
    Type: Application
    Filed: July 11, 2022
    Publication date: January 11, 2024
    Applicant: Xilinx, Inc.
    Inventors: Shantanu Mishra, Hemant Kashyap, Uday Kyatham, Mahesh Attarde, Amit Kasat Kasat