Patents by Inventor Shantanu SARANGI
Shantanu SARANGI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240132083Abstract: Systems and methods are disclosed that relate to testing processing elements of an integrated processing system. A first system test may be performed on a first processing element of an integrated processing system. The first system test may be based at least on accessing a test node associated with the first processing element. The first system test may be accessed using a first local test controller. A second system test may be performed on a second processing element of the integrated processing system. The second system test may be based at least on accessing a second test node associated with the second processing element. The second system test may be accessed using a second local test controller.Type: ApplicationFiled: October 23, 2022Publication date: April 25, 2024Inventors: Anitha Kalva, Jae Wu, Shantanu Sarangi, Sailendra Chadalavada, Milind Sonawane, Chen Fang, Abilash Nerallapally
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Patent number: 11867744Abstract: Techniques for isolating interfaces while testing a semiconductor device include a semiconductor device having a link interface that couples the semiconductor device to a high-speed data transfer link, a clock control unit that transmits one or more clock signals to the link interface; and a protection module. The protection module asserts a clock stop request to the clock control unit and, in response to receiving a clock stop acknowledgement from the clock control unit, asserts a clamp enable to cause the link interface to be isolated from portions of the semiconductor device. After waiting for a first predetermined period of time to expire, the protection module de-asserts the clock stop request.Type: GrantFiled: October 20, 2020Date of Patent: January 9, 2024Assignee: NVIDIA CorporationInventors: Animesh Khare, Ashish Kumar, Shantanu Sarangi, Rahul Garg, Sailendra Chadalavada
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Publication number: 20230349970Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.Type: ApplicationFiled: July 6, 2023Publication date: November 2, 2023Inventors: Shantanu Sarangi, Jae Wu, Andi Skende, Rajith Mavila
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Patent number: 11726139Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.Type: GrantFiled: August 8, 2022Date of Patent: August 15, 2023Assignee: NVIDIA CorporationInventors: Shantanu Sarangi, Jae Wu, Andi Skende, Rajith Mavila
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Patent number: 11668750Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.Type: GrantFiled: September 17, 2021Date of Patent: June 6, 2023Assignee: NVIDIA CORPORATIONInventors: Sailendra Chadalavada, Venkat Abilash Reddy Nerallapally, Jaison Daniel Kurien, Bonita Bhaskaran, Milind Sonawane, Shantanu Sarangi, Purnabha Majumder
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Publication number: 20230146920Abstract: Introduced herein is a technique that reliably measures on-die noise of logic in a chip. The introduced technique places a noise measurement system in partitions of the chip that are expected to cause the most noise. The introduced technique utilizes a continuous free-running clock that feeds functional frequency to the noise measurement circuit throughout the noise measurement scan test. This allows the noise measurement circuit to measure the voltage noise of the logic during a shift phase, which was not possible in the conventional noise measurement method. Also, by being able to measure the voltage noise during a shift phase and hence in both phases of the scan test, the introduced technique can perform a more comprehensive noise measurement not only during ATE testing but as part of IST in the field.Type: ApplicationFiled: November 2, 2022Publication date: May 11, 2023Inventors: Bonita Bhaskaran, Nithin Valentine, Shantanu Sarangi, Mahmut Yilmaz, Suhas Satheesh, Charlie Hwang, Tezaswi Raja, Kevin Zhou, Sailendra Chadalavada, Kevin Ye, Seyed Nima Mozaffari Mojaveri, Kerwin Fu
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Publication number: 20230123956Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.Type: ApplicationFiled: December 20, 2022Publication date: April 20, 2023Inventors: Jonah Alben, Sachin Idgunji, Jue Wu, Shantanu Sarangi
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Publication number: 20230089800Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements, a selected independent processing element is taken offline and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation. To minimize voltage drops resulting from current fluctuations produced by the testing of the processing element, clocks used to synchronize operations within each partition of a processing element are staggered. This varies the toggle rate within each partition of the processing element during the testing of the processing core, thereby reducing the resulting voltage drop. This may also improve test quality within an automated test equipment (ATE) environment.Type: ApplicationFiled: September 17, 2021Publication date: March 23, 2023Inventors: Sailendra Chadalavada, Venkat Abilash Reddy Nerallapally, Jaison Daniel Kurien, Bonita Bhaskaran, Milind Sonawane, Shantanu Sarangi, Purnabha Majumder
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Patent number: 11573872Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.Type: GrantFiled: December 20, 2021Date of Patent: February 7, 2023Assignee: NVIDIA CorporationInventors: Jonah Alben, Sachin Idgunji, Jue Wu, Shantanu Sarangi
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Patent number: 11526644Abstract: The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.Type: GrantFiled: November 5, 2020Date of Patent: December 13, 2022Assignee: NVIDIA CorporationInventors: Kaushik Narayanun, Mahmut Yilmaz, Shantanu Sarangi, Jae Wu
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Publication number: 20220382659Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.Type: ApplicationFiled: August 8, 2022Publication date: December 1, 2022Inventors: Shantanu Sarangi, Jae Wu, Andi Skende, Rajith Mavila
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Publication number: 20220365857Abstract: During functional/normal operation of an integrated circuit including multiple independent processing elements (such as processors), a selected independent processing element is taken offline (e.g., by stopping functional operation of the independent processing element), and the functionality of the selected independent processing element is then tested while the remaining independent processing elements continue functional operation (e.g., standard application-specific operations). This enables the selected processing element to be robustly tested without stopping the regular operation of the integrated circuit.Type: ApplicationFiled: May 13, 2021Publication date: November 17, 2022Inventors: Sailendra Chadalavada, Anitha Kalva, Abilash Nerallapally, Milind Sonawane, Shantanu Sarangi, Ashok Aravamudhan, Sridharan Ramakrishnan, Sam Edirisooriya, Hari Krishnan
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Patent number: 11408934Abstract: Manufacturers perform tests on chips before the chips are shipped to customers. However, defects can occur on a chip after the manufacturer testing and when the chips are used in a system or device. The defects can occur due to aging or the environment in which the chip is employed and can be critical; especially when the chips are used in systems such as autonomous vehicles. To verify the structural integrity of the IC during the lifetime of the product, an in-system test (IST) is disclosed. The IST enables self-testing mechanisms for an IC in working systems. The IST mechanisms provide structural testing of the ICs when in a functional system and at a manufacturer's level of testing. Unlike ATE tests that are running on a separate environment, the IST provides the ability to go from a functional world view to a test mode.Type: GrantFiled: December 21, 2018Date of Patent: August 9, 2022Assignee: Nvidia CorporationInventors: Shantanu Sarangi, Jae Wu, Andi Skende, Rajith Mavila
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Publication number: 20220138387Abstract: The disclosure provides using test processors to provide a more flexible solution compared to the existing DFX blocks that are used for controlling test networks in chips. The test processors provide a highly flexible solution since programming of the test processors can be changed at any time; even after manufacturing, and can support practically an unlimited number of core chips in any configuration. The high flexibility provided via the test processors can reduce engineering effort needed in design and verification, accelerate schedules, and may prevent additional tapeouts in case of DFX design bugs. By making debug and diagnosis easier by providing an opportunity to change debug behavior as needed, the time-to-market timeline can be accelerated. Accordingly, the disclosure provides a chip with a test processor, a multi-chip processing system with a test processor, and a method of designing a chip having a test processor.Type: ApplicationFiled: November 5, 2020Publication date: May 5, 2022Inventors: Kaushik Narayanun, Mahmut Yilmaz, Shantanu Sarangi, Jae Wu
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Publication number: 20220121542Abstract: Techniques for testing semiconductor devices include a semiconductor device having a plurality of components, a test bus, and a test data transfer unit. The test data transfer unit receives, from a host computer, configuration information for performing a test of the semiconductor device, reads, via a high-speed data transfer link, test data associated with the test from memory of the host computer using direct memory access, sends the test data to the plurality of components via the test bus, causes one or more operations to be performed on the semiconductor device to effect at least a portion of the test, and after the one or more operations have completed, retrieves test results of the at least a portion of the test from the test bus and stores, via the high-speed data transfer link, the test results in the memory of the host computer using direct memory access.Type: ApplicationFiled: October 20, 2020Publication date: April 21, 2022Inventors: Animesh KHARE, Ashish KUMAR, Shantanu SARANGI, Rahul GARG
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Publication number: 20220120804Abstract: Techniques for isolating interfaces while testing a semiconductor device include a semiconductor device having a link interface that couples the semiconductor device to a high-speed data transfer link, a clock control unit that transmits one or more clock signals to the link interface; and a protection module. The protection module asserts a clock stop request to the clock control unit and, in response to receiving a clock stop acknowledgement from the clock control unit, asserts a clamp enable to cause the link interface to be isolated from portions of the semiconductor device. After waiting for a first predetermined period of time to expire, the protection module de-asserts the clock stop request.Type: ApplicationFiled: October 20, 2020Publication date: April 21, 2022Inventors: Animesh KHARE, Ashish KUMAR, Shantanu SARANGI, Rahul GARG, Sailendra CHADALAVADA
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Publication number: 20220114069Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.Type: ApplicationFiled: December 20, 2021Publication date: April 14, 2022Inventors: Jonah ALBEN, Sachin Idgunji, Jue Wu, Shantanu Sarangi
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Patent number: 11204849Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.Type: GrantFiled: March 13, 2020Date of Patent: December 21, 2021Assignee: NVIDIA CorporationInventors: Jonah Alben, Sachin Idgunji, Jue Wu, Shantanu Sarangi
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Publication number: 20210286693Abstract: In various examples, one or more components or regions of a processing unit—such as a processing core, and/or component thereof—may be tested for faults during deployment in the field. To perform testing while in deployment, the state of a component subject to test may be retrieved and/or stored during the test to maintain state integrity, the component may be clamped to communicatively isolate the component from other components of the processing unit, a test vector may be applied to the component, and the output of the component may be compared against an expected output to determine if any faults are present. The state of the component may be restored after testing, and the clamp removed, thereby returning the component to its operating state without a perceivable detriment to operation of the processing unit in deployment.Type: ApplicationFiled: March 13, 2020Publication date: September 16, 2021Inventors: Jonah ALBEN, Sachin Idgunji, Jue Wu, Shantanu Sarangi
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Patent number: 10663515Abstract: A hardware controller of a device under test (DUT) communicates with a PCIe controller to fetch test data and control test execution. The hardware controller also communicates with a JTAG/IEEE 1500 component to set up the DUT into various test configurations and to trigger test execution. For SCAN tests, the hardware controller provides a high throughput direct access to the on-chip compressors/decompressors to load the scan data and to collect the test results.Type: GrantFiled: October 30, 2018Date of Patent: May 26, 2020Assignee: NVIDIA Corp.Inventors: Kaushik Narayanun, Shantanu Sarangi