Abstract: Apparatus and methods for interfacing with a micro-electromechanical system (MEMS) sensor are provided. In an example, an apparatus can interface circuit including an integrator circuit, a sample switch circuit, a saturation detector and a controller. The saturation detector can be configured to receive a signal indicative of an integration of charge of the sensor, to compare the signal indicative of the integration of charge to an integrator saturation threshold and to modulate a divide parameter using the comparison of the signal indicative of the integration of charge and the integrator saturation threshold. The controller can be configured to receive a clock signal and to control the sample switch circuit based on a phase of the clock signal and the divide parameter.

Abstract: This application discusses simplified interface circuits for a gyroscope. In an example, an interface can include an automatic gain control (AGC) circuit configured to couple to driver for a proof mass of a gyroscope sensor and to drive the proof-mass to oscillate at a predefined oscillation amplitude, and a phase-locked loop (PLL) configured to receive sensed oscillation information from the proof-mass and to provide at least a first phase signal synchronized with a sinusoidal waveform of the sensed oscillation information.

Abstract: This application discusses, among other things, simplified interface circuits for a gyroscope. In an example, a interface can include an automatic gain control (AGC) circuit configured to couple to driver for a proof mass of a gyroscope sensor and to drive the proof-mass to oscillate at a predefined oscillation amplitude, and a phase-locked loop (PLL) configured to receive sensed oscillation information from the proof-mass and to provide at least a first phase signal synchronized with a sinusoidal waveform of the sensed oscillation information.

Abstract: Apparatus and methods for interfacing with a micro-electromechanical system (MEMS) sensor are provided. In an example, an apparatus can interface circuit including an integrator circuit, a sample switch circuit, a saturation detector and a controller. The saturation detector can be configured to receive a signal indicative of an integration of charge of the sensor, to compare the signal indicative of the integration of charge to an integrator saturation threshold and to modulate a divide parameter using the comparison of the signal indicative of the integration of charge and the integrator saturation threshold. The controller can be configured to receive a clock signal and to control the sample switch circuit based on a phase of the clock signal and the divide parameter.

Abstract: A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred embodiment of the current invention may be deployed in a clockless configuration. Preferably, one or more controllable analog filters may be controlled by one or more microprocessors used to assess the error data from the error generators and to calculate the appropriate coefficients for the filters according to one or more error minimization algorithms. Preferably, the steps of sampling, assessment, calculation and coefficient setting may be done iteratively to converge to an optimum set of filter values and/or respond dynamically to signals with time-varying noise and interference characteristics.

Abstract: Methods, apparatuses, and systems are presented for performing channel equalization comprising receiving a signal from a channel associated with inter-symbol interference, processing the received signal to effectively apply a plurality of linearly independent impulse responses to the received signal to produce a plurality of intermediate signals, scaling each of the intermediate signals by each of a plurality of multiplier factors to produce a plurality of scaled signals, and combining the scaled signals to produce a resulting signal corresponding to an equalized version of the received signal in order to reduce effects of inter-symbol interference.

Abstract: A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred embodiment of the current invention may be deployed in a clockless configuration. Preferably, one or more controllable analog filters may be controlled by one or more microprocessors used to assess the error data from the error generators and to calculate the appropriate coefficients for the filters according to one or more error minimization algorithms. Preferably, the steps of sampling, assessment, calculation and coefficient setting may be done iteratively to converge to an optimum set of filter values and/or respond dynamically to signals with time-varying noise and interference characteristics.

Abstract: A method and apparatus for improved high-speed adaptive equalization that may operate effectively even in systems experiencing severe interference by using one or more error generators and taking multiple samples across a bit interval. Advantageously, a preferred embodiment of the current invention may be deployed in a clockless configuration. Preferably, one or more controllable analog filters may be controlled by one or more microprocessors used to assess the error data from the error generators and to calculate the appropriate coefficients for the filters according to one or more error minimization algorithms. Preferably, the steps of sampling, assessment, calculation and coefficient setting may be done iteratively to converge to an optimum set of filter values and/or respond dynamically to signals with time-varying noise and interference characteristics.

Abstract: Methods, apparatuses, and systems are presented for performing channel equalization involving receiving a signal from a channel associated with inter-s interference (ISI), providing the received signal to an inductor, capacitor, resistance (LCR) network comprising a plurality of inductors and a plurality of capacitors, generating in the LCR network a first plurality of intermediate signals representing voltages associated with capacitors in the LCR network and a second plurality of intermediate signals representing currents associated with inductors in the LCR network, wherein the first plurality and second plurality of intermediate signals correspond to application of linearly independent impulse responses to the received signal, applying a corresponding one of a plurality of multiplier factors to each of the first plurality and second plurality of intermediate signals, and generating from the LCR network a resulting signal corresponding to an equalized version of the received signal.

Abstract: Improved high-speed adaptive equalization is presented that may involve converting an optical signal into an electrical signal and performing equalization by (i) filtering the electrical signal with an analog filter according to at least one filter coefficient to produce a filtered output, (ii) generating an error signal from the filtered output according to an error function, (iii) providing at least one control signal to the analog filter for adjusting the at least one filter coefficient, (iv) detecting a relationship between a change in the at least one filter coefficient and a change in the error signal, and (v) adjusting the at least one filter coefficient according to the relationship to minimize the error signal. The least one coefficient may comprise a plurality of coefficients, and the relationship may be a gradient estimate having multiple components, each determined by varying only one of the coefficients and detecting a resulting change in the error signal.

Abstract: Methods, apparatuses, and systems are presented for performing channel equalization involving receiving a signal from a channel associated with inter-symbol interference (ISI), providing the received signal to an LCR network comprising a plurality of inductors and a plurality of capacitors, generating in the LCR network a first plurality of intermediate signals representing voltages associated with capacitors in the LCR network and a second plurality of intermediate signals representing currents associated with inductors in the LCR network, wherein the first plurality and second plurality of intermediate signals correspond to application of linearly independent impulse responses to the received signal, applying a corresponding one of a plurality of multiplier factors to each of the first plurality and second plurality of intermediate signals, and generating from the LCR network a resulting signal corresponding to an equalized version of the received signal.

Abstract: Methods, apparatuses, and systems are presented for performing channel equalization comprising receiving a signal from a channel associated with inter-symbol interference, processing the received signal to effectively apply a plurality of linearly independent impulse responses to the received signal to produce a plurality of intermediate signals, scaling each of the intermediate signals by each of a plurality of multiplier factors to produce a plurality of scaled signals, and combining the scaled signals to produce a resulting signal corresponding to an equalized version of the received signal in order to reduce effects of inter-symbol interference.

Abstract: Improved high-speed adaptive equalization is presented that may involve converting an optical signal into an electrical signal and performing equalization by (i) filtering the electrical signal with an analog filter according to at least one filter coefficient to produce a filtered output, (ii) generating an error signal from the filtered output according to an error function, (iii) providing at least one control signal to the analog filter for adjusting the at least one filter coefficient, (iv) detecting a relationship between a change in the at least one filter coefficient and a change in the error signal, and (v) adjusting the at least one filter coefficient according to the relationship to minimize the error signal. The least one coefficient may comprise a plurality of coefficients, and the relationship may be a gradient estimate having multiple components, each determined by varying only one of the coefficients and detecting a resulting change in the error signal.

Abstract: A method and system to compensate for DC and low frequency current produced by a photodiode that is illuminated with an optical data stream is described. An optical data stream ideally produces no current from a photodiode when the bit is a 0 and produces a current proportional to the optical power when the bit is a 1. Thus, the current produced from the photodiode consists of a DC component, which is typically half the current of a 1 bit (if there is an equal number of 1s and 0s in the data), and a high frequency component that carries the data. The DC component can interfere with the signal path's ability to process the information carrying component of the photodiode current, by causing a fixed offset to propagate and be amplified through it. This offset distorts the voltage signal at the output of the signal path, and must therefore be cancelled early in the path; usually in the first transimpedance stage or just after it.

Abstract: Method and system for a programmable analog tapped delay line filter are disclosed. One embodiment of the present invention is a programmable analog tapped delay line filter comprising an input line, an output line, and one or more gaincells or taps coupled between the input line and the output line. The input and output lines each comprises a cascade of one or more differential delay cells, and each of the one or more gaincells or taps corresponds to a tap weight or coefficient. Furthermore, the input and output lines are terminated in impedances and the filter produces one or more outputs.

Abstract: A transconductance bias circuit includes: a differential pair having a first transistor M14 and a second transistor M15; a resistor R coupled between a gate of the first transistor M14 and a gate of the second transistor M15, the gate of the first transistor M14 is coupled to a reference voltage node; a third transistor M10 coupled to the first transistor M14; a fourth transistor M11 coupled to the second transistor M15; a fifth transistor M8 coupled to the third transistor M10, a gate of the fifth transistor M8 is coupled to the reference voltage node; a sixth transistor M9 coupled to the fourth transistor M11, a gate of the sixth transistor M9 is coupled to the reference voltage node; a current mirror 22 coupled to the fifth and sixth transistors M8 and M9; and a seventh transistor M6 coupled to the fourth transistor M11, a current in the seventh transistor M6 is equal to a current in the resistor R.

Abstract: A circuit 100, which can be used to perform a sample and hold function, includes a switch 112 with a current patch coupled between an input node VIN and an output node VOUT. A capacitor 114 is coupled to the output node VOUT. A replica device 160 includes a current path coupled between the input node VIN and a supply voltage node VDD. A bootstrap circuit, e.g., including a bootstrap capacitor 164, is coupled between a control terminal of the first switch 112 and a control terminal of the replica device 160.

Abstract: A transconductance bias circuit includes: a differential pair having a first transistor M14 and a second transistor M15; a resistor R coupled between a gate of the first transistor M14 and a gate of the second transistor M15, the gate of the first transistor M14 is coupled to a reference voltage node; a third transistor M10 coupled to the first transistor M14; a fourth transistor M11 coupled to the second transistor M15; a fifth transistor M8 coupled to the third transistor M10, a gate of the fifth transistor M8 is coupled to the reference voltage node; a sixth transistor M9 coupled to the fourth transistor M11, a gate of the sixth transistor M9 is coupled to the reference voltage node; a current mirror 22 coupled to the fifth and sixth transistors M8 and M9; and a seventh transistor M6 coupled to the fourth transistor M11, a current in the seventh transistor M6 is equal to a current in the resistor R.