Abstract: An apparatus is described and includes a packet reordering engine (PRE) for reordering data packets stored in a packet buffer at locations identified by buffer descriptors (BD). The PRE includes a BD fetch manager for fetching BDs associated with the stored data packets; a header decoder module for fetching the header portion for the stored data packets associated with the fetched BDs; a reorder module for receiving the fetched BDs and the fetched header portions and storing the fetched BD associated with the data packet in a slot of the reorder buffer; and a buffer processor configured to receive BDs from the reorder module in an order indicated by the header information of the data packets associate with the BDs and to fetch the payloads of the data packets with which the received BDs are associated from the packet buffer.

Abstract: Systems and methods for converting images, such as JPEG images. Decoded image data is produced in block format having minimum coded units (MCUs). The blocks each include a square of pixels and are stored in linear format in memory. A block to burst converter is provided that receives a set of image blocks, stores partial rows of a frame locally, and then writes out each partial row in a burst of raster blocks. The systems and methods provided herein reduce local memory use by orders of magnitude while also reducing system latency.

Abstract: A digital log gain to digital linear gain multiplier is disclosed. The digital log gain to digital linear gain multiplier includes a log gain splitter adapted to split a log gain input into an integer log part and a remainder log part. A log scale-to-linear scale converter is adapted to output a linear gain value in response to the integer log part and the remainder log part. A gain multiply circuit is adapted to multiply a digital signal by the linear gain value to output a gain-enhanced digital signal.

Abstract: A digital log gain to digital linear gain multiplier is disclosed. The digital log gain to digital linear gain multiplier includes a log gain splitter adapted to split a log gain input into an integer log part and a remainder log part. A log scale-to-linear scale converter is adapted to output a linear gain value in response to the integer log part and the remainder log part. A gain multiply circuit is adapted to multiply a digital signal by the linear gain value to output a gain-enhanced digital signal.