Patents by Inventor Shanthi SUDALAIYANDI

Shanthi SUDALAIYANDI has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Digital delay locked loop
    Patent number: 10666270
    Abstract: The invention concerns a digital delay locked loop comprising: first and second digitally controllable delay lines (202B, 204B) coupled in series with each other, each comprising a lead portion (214, 218) and a lag portion (216, 220), the first digitally controllable delay line receiving a reference timing signal (TREF) and the second digitally controllable delay line outputting a delayed timing signal (TREF); and a time to digital converter (212) configured to evaluate a phase difference between the reference signal (TREF) and the delayed timing signal (TREF?) and to generate a first control signal (DLEAD_[0:n]) for controlling said lead portions (214, 218) or a second control signal (DLAG[0:n]) for controlling said lag portions (216, 220) based on the sign and magnitude of the phase difference.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: May 26, 2020
    Assignee: COMMISSARIAT Á L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Shanthi Sudalaiyandi, Gilles Masson, Michaël Pelissier, Mykhailo Zarudniev
  • DIGITAL DELAY LOCKED LOOP
    Publication number: 20190199361
    Abstract: The invention concerns a digital delay locked loop comprising: first and second digitally controllable delay lines (202B, 204B) coupled in series with each other, each comprising a lead portion (214, 218) and a lag portion (216, 220), the first digitally controllable delay line receiving a reference timing signal (TREF) and the second digitally controllable delay line outputting a delayed timing signal (TREF); and a time to digital converter (212) configured to evaluate a phase difference between the reference signal (TREF) and the delayed timing signal (TREF?) and to generate a first control signal (DLEAD_[0:n]) for controlling said lead portions (214, 218) or a second control signal (DLAG[0:n]) for controlling said lag portions (216, 220) based on the sign and magnitude of the phase difference.
    Type: Application
    Filed: December 21, 2018
    Publication date: June 27, 2019
    Inventors: Shanthi SUDALAIYANDI, Gilles MASSON, Michaël PELISSIER, Mykhailo ZARUDNIEV