Patents by Inventor Shantilal Rayshi Doru

Shantilal Rayshi Doru has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240161836
    Abstract: Described are systems and methods for memory read threshold tracking based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first value of a metric characterizing threshold voltage distributions of a subset of a set of the plurality of memory cells; determining a first voltage threshold adjustment value; receiving a second value of the metric; determining a second voltage threshold adjustment value; and applying the second voltage threshold adjustment value for reading the set of the plurality of memory cells.
    Type: Application
    Filed: November 13, 2023
    Publication date: May 16, 2024
    Inventors: Shantilal Rayshi Doru, Patrick R. Khayat, Steven Michael Kientz, Sampath K. Ratnam, Dung Viet Nguyen
  • Publication number: 20240069788
    Abstract: In some implementations, a controller of a memory device may obtain a first metric associated with a memory of the memory device using a first memory read configuration. The controller may apply a function to the first metric to obtain a second memory read configuration. The controller may obtain a second metric associated with the memory using the second memory read configuration. The controller may filter the first metric and the second metric to obtain a first filtered metric and a second filtered metric. The controller may provide the first filtered metric and the second filtered metric to a memory management process executing on the controller. The controller may perform an action based on an output of the memory management process, wherein the output is based on the first filtered metric and the second filtered metric.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Dung Viet NGUYEN, Shantilal Rayshi DORU, Jun WAN, Sampath RATNAM
  • Publication number: 20240029801
    Abstract: Described are systems and methods for memory read calibration based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first metric characterizing threshold voltage distributions of a subset of the plurality of memory cells; determining a first read voltage adjustment; receiving a second metric characterizing the threshold voltage distributions; determining a second read voltage adjustment; and applying the second read voltage adjustment for reading the subset of the plurality of memory cells.
    Type: Application
    Filed: June 20, 2023
    Publication date: January 25, 2024
    Inventors: Dung Viet Nguyen, Patrick R. Khayat, Zhengang Chen, Shantilal Rayshi Doru, Hope Abigail Henry