Patents by Inventor Shanto A. Thomas

Shanto A. Thomas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10734393
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.
    Type: Grant
    Filed: November 7, 2018
    Date of Patent: August 4, 2020
    Assignee: Intel Corporation
    Inventors: Navneet K. Singh, Shanto A. Thomas, Ranjul Balakrishnan
  • Publication number: 20190074281
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.
    Type: Application
    Filed: November 7, 2018
    Publication date: March 7, 2019
    Applicant: Intel Corporation
    Inventors: Navneet K. Singh, Shanto A. Thomas, Ranjul Balakrishnan
  • Patent number: 10177161
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: January 8, 2019
    Assignee: Intel Corporation
    Inventors: Navneet K. Singh, Shanto A. Thomas, Ranjul Balakrishnan
  • Publication number: 20180182734
    Abstract: Methods of forming microelectronic package structures, and structures formed thereby, are described. Those methods/structures may include attaching a die on a board, attaching a substrate on the die, wherein the substrate comprises a first region and a peripheral region, attaching a first memory device on the central region of the substrate, and attaching at least one additional memory device on the peripheral region of the substrate, wherein the at least one additional memory device is not disposed over the die.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Applicant: Intel Corporation
    Inventors: Navneet K. Singh, Shanto A. Thomas, Ranjul Balakrishnan
  • Publication number: 20140065881
    Abstract: Embodiments of apparatus, methods, systems, devices, and connectors are described herein for a connector having a longitudinal body configured to mount the connector to a PCB. In various embodiments, a first and a second socket may be respectively disposed at a first side and a second side of the longitudinal body. In various embodiments, the first and second sockets may removably receive a first memory module from a first direction and a second memory module from a second direction opposite to the first direction. In various embodiments, the second side may be opposite to the first side. In various embodiments, on insertion into the first and second sockets, the first and second memory modules may be coplanar and/or equidistant from the PCB along a third direction orthogonal to the first and second directions.
    Type: Application
    Filed: September 4, 2012
    Publication date: March 6, 2014
    Inventors: S. Vinay, Ramaswamy Parthasarathy, Shivaprasad Chandramouli, Shanto A. Thomas, Vikas Rao, Aruljothi Kandasamy