Patents by Inventor Shantonu Bhadury

Shantonu Bhadury has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11200930
    Abstract: A memory system including a memory device, cache controller circuitry, and timing circuitry. The memory device has a read enable input for receiving a read enable indication for requesting stored data, and has a minimum delay specification between consecutive read enable indications. The cache controller circuitry provides a read indication during a prefetch mode to read data from a next linear address from the memory device, provides a reading indication while data is being read, and provides a miss indication when a next processor address is not the next linear address. The timing circuitry includes synchronization circuitry receiving the read indication and a clock signal and provides a preliminary read enable indication, read enable circuitry receiving a mask indication and the preliminary read enable indication and providing the read enable indication, and mask circuitry that provides the mask indication when the reading indication and the miss indication are both provided.
    Type: Grant
    Filed: December 2, 2020
    Date of Patent: December 14, 2021
    Assignee: Silicon Laboratories Inc.
    Inventors: Harikrishnan Prabha Valsala, Hong Lee Koo, Shantonu Bhadury
  • Patent number: 10222421
    Abstract: Embodiments are disclosed for systems and methods that include pulsing a clock pin of retention cells included within a scan chain to shift a sequence of logic values into the scan chain, so that successive cells are loaded with opposite logic values. Embodiments also include pulsing a retain pin to retain the logic values, and pulsing the clock pin to shift the sequence of logic values through the chain, so that retained logic values are output from, and logic values opposite to the retained logic values are loaded into, the cells. Embodiments also include pulsing a restore pin to restore the retained logic values, pulsing the clock pin to shift the logic values out of the scan chain, comparing the logic values shifted out of the scan chain with the logic values shifted into the scan chain, and detecting a fault on the retain pin based on said comparison.
    Type: Grant
    Filed: February 14, 2018
    Date of Patent: March 5, 2019
    Assignee: Silicon Laboratories Inc.
    Inventors: Mudit Srivastava, Raghavendra Pai Kateel, Shantonu Bhadury
  • Patent number: 8502801
    Abstract: A method of matrix sensing using delay-based capacitance sensing, including using X-axis lines as active lines for capacitance measurements and using Y-axis lines as a disturbance to identify the location of a touch in a key matrix is disclosed. A sensing signal is applied to the X-axis lines, and a disturbance signal is applied to the Y-axis lines. If a location is touched, cross-capacitance is reduced, which is measured by sweeping data along the X-axis lines.
    Type: Grant
    Filed: April 23, 2009
    Date of Patent: August 6, 2013
    Assignee: STMicroelectronics Asia Pacific Pte Ltd.
    Inventors: Hup-Peng Goh, Shantonu Bhadury, Kusuma Adi Ningrat, Chee Yu Ng, Giuseppe Noviello
  • Publication number: 20120054379
    Abstract: An integrated control circuit is disclosed including a central processing unit operating in a normal full system power mode and in a reduced system low power mode, and a memory. A plurality of peripheral units are provided, at least one of which includes an input/output for interfacing with at least an external system for receiving information therefrom and a process block. The process block processes the received information from the external system and during the processing of the received information, data is stored in the at least one peripheral unit, and data is transferred at least to or at least from the memory. The input/output and process blocks are fully operable in the full system power mode and the reduced system power mode. A direct memory access (DMA) transfers data directly between the at least one peripheral and the memory when such data transfer is required by the peripheral.
    Type: Application
    Filed: August 30, 2010
    Publication date: March 1, 2012
    Inventors: Kafai Leung, Brent Wilson, Yonghong Tao, Shan Wang, Shantonu Bhadury, Suby Pellissery, Raghavendra Pai Kateel, David Welland, David Andreas, Gabriel Vogel
  • Publication number: 20100053097
    Abstract: A method of matrix sensing using delay-based capacitance sensing, including using X-axis lines as active lines for capacitance measurements and using Y-axis lines as a disturbance to identify the location of a touch in a key matrix is disclosed. A sensing signal is applied to the X-axis lines, and a disturbance signal is applied to the Y-axis lines. If a location is touched, cross-capacitance is reduced, which is measured by sweeping data along the X-axis lines.
    Type: Application
    Filed: April 23, 2009
    Publication date: March 4, 2010
    Applicant: STMicroelectronics Asia Pacific Pte Ltd.
    Inventors: Hup-Peng Goh, Shantonu Bhadury, Kusuma Adi Ningrat, Chee Yu Ng, Giuseppe Noviello