Patents by Inventor Shao Chee Ong

Shao Chee Ong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Bit error rate testing for high-speed devices
    Patent number: 7308371
    Abstract: A method and system for performing a bit error rate test on a device with substantial duty cycle output distortion are described herein.
    Type: Grant
    Filed: June 15, 2004
    Date of Patent: December 11, 2007
    Assignee: Intel Corporation
    Inventor: Shao Chee Ong
  • High-speed duty cycle test through DC measurement using a combination of relays
    Patent number: 6943556
    Abstract: According to one embodiment of the present invention, a method of high-speed duty cycle test through DC measurement using a combination of relays. The method includes: providing a plurality of relays to generate one or more duty cycle control signals; providing the duty cycle control signals to a device under test; measuring a first DC portion of a first output signal of the device under test; and dividing the first DC portion by a sum of the first DC portion and a second DC portion of a second output signal of the device under test.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: September 13, 2005
    Assignee: Intel Corporation
    Inventor: Shao Chee Ong
  • High-speed duty cycle test through DC measurement using a combination of relays
    Publication number: 20040263184
    Abstract: According to one embodiment of the present invention, a method of high-speed duty cycle test through DC measurement using a combination of relays. The method includes: providing a plurality of relays to generate one or more duty cycle control signals; providing the duty cycle control signals to a device under test; measuring a first DC portion of a first output signal of the device under test; and dividing the first DC portion by a sum of the first DC portion and a second DC portion of a second output signal of the device under test.
    Type: Application
    Filed: June 30, 2003
    Publication date: December 30, 2004
    Inventor: Shao Chee Ong