Patents by Inventor Shao-Cheng Hsiao

Shao-Cheng Hsiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11128264
    Abstract: A bias compensation circuit, coupled to an amplifying transistor, is disclosed. The bias compensation circuit comprises a voltage locking circuit, comprising a first terminal and a second terminal, wherein the first terminal is coupled to a third terminal the amplifying transistor, and the second terminal is coupled to a control terminal of the amplifying transistor; and a first resistor, coupled to the first terminal of the voltage locking circuit; wherein when the voltage locking circuit is conducted, a voltage difference between the first terminal and the second terminal is substantially constant.
    Type: Grant
    Filed: April 19, 2020
    Date of Patent: September 21, 2021
    Assignee: WIN Semiconductors Corp.
    Inventors: Po-Kie Tseng, Chih-Wen Huang, Jui-Chieh Chiu, Shao-Cheng Hsiao
  • Publication number: 20210288612
    Abstract: A bias compensation circuit, coupled to an amplifying circuit, is disclosed. The bias compensation circuit comprises a transistor, comprising a first terminal, a second terminal and a control terminal; a first feedback transistor, comprising a control terminal, coupled to the first terminal of the transistor; a first terminal, coupled to the control terminal of the transistor; and a second terminal; and a second feedback transistor, comprising a control terminal, coupled to the first terminal of the transistor; a first terminal, coupled to the amplifying circuit; and a second terminal; and a first resistor, comprising a first terminal, coupled to the first terminal of the transistor; and a second terminal, configured to receive a first voltage.
    Type: Application
    Filed: March 12, 2020
    Publication date: September 16, 2021
    Inventors: Po-Kie Tseng, Chih-Wen Huang, Jui-Chieh Chiu, Shao-Cheng Hsiao
  • Publication number: 20210257319
    Abstract: A gallium arsenide (GaAs) radio frequency (RF) circuit is disclosed. The GaAs RF circuit includes a power amplifier and a low noise amplifier; a first transmit/receive (TR) switch, coupled to the power amplifier and the low noise amplifier, wherein the first TR switch is fabricated by a pHEMT (Pseudomorphic High Electron Mobility Transistor) process; and a first active phase shifter, coupled to the power amplifier or the low noise amplifier, wherein the first active phase shifter is fabricated by an HBT (Heterojunction Bipolar Transistor) process; wherein the GaAs RF circuit is formed within a GaAs die.
    Type: Application
    Filed: February 14, 2020
    Publication date: August 19, 2021
    Inventors: Shao-Cheng Hsiao, Chih-Wen Huang, Jui-Chieh Chiu, Po-Kie Tseng
  • Patent number: 10580768
    Abstract: A GaAs (Gallium Arsenide) cell is provided. The GaAs cell comprises at least a GaAs substrates; a plurality of drain electrodes and a plurality of source electrodes, disposed on the at least a GaAs substrates; a gate electrode, disposed between the plurality of drain electrodes and the plurality of source electrodes, elongated along a first direction; a first anchor at a first end of the gate electrode; and a second anchor at a second end of the gate electrode; wherein a gate length of the gate electrode on a second direction is smaller than both a first width of the first anchor and a second width of the second anchor along the second direction.
    Type: Grant
    Filed: September 28, 2018
    Date of Patent: March 3, 2020
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, Shao-Cheng Hsiao
  • Patent number: 10432200
    Abstract: A GaAs (Gallium Arsenide) cell is provided. The GaAs cell comprises a drain electrode and a source electrode, disposed on the GaAs substrate; a plurality of gate electrodes, disposed between the drain electrode and the source electrode, elongated on a first direction, wherein a gate electrode among the plurality of gate electrodes comprises a first end and a second end; a plurality of first anchors; a plurality of second anchors; wherein a first gate electrode and a second gate electrode among the plurality of gate electrodes are spaced by a gate-to-gate spacing, the first gate electrode and the drain electrode are spaced by a first gate-to-terminal spacing, and the gate-to-gate spacing is smaller than twice of the first gate-to-terminal spacing.
    Type: Grant
    Filed: November 15, 2018
    Date of Patent: October 1, 2019
    Assignee: WIN Semiconductors Corp.
    Inventors: Jui-Chieh Chiu, Chih-Wen Huang, Shao-Cheng Hsiao