Patents by Inventor Shao-Ching Liao
Shao-Ching Liao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10475513Abstract: A resistive memory and a resistance window recovery method for a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between a top electrode and a bottom electrode of the resistive memory cell, wherein the over reset voltage difference falls in a reset complementary switching (reset-CS) voltage range of the resistive memory cell. During a second period, a set voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell to increase a compliance current of the resistive memory cell. During a third period, a reset operation is performed on the resistive memory cell.Type: GrantFiled: June 5, 2018Date of Patent: November 12, 2019Assignee: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Shao-Ching Liao, Ming-Che Lin, Min-Chih Wei, Chuan-Sheng Chou
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Publication number: 20190221260Abstract: A power on reset method for a resistive memory storage device is provided and includes performing a forming procedure on a memory cell of the resistive memory storage device. The forming procedure includes applying at least one forming voltage and at least one reset voltage to the memory cell. The forming procedure further includes a thermal step. The step of applying at least one reset voltage to the memory cell may be preformed before or after the thermal step. After one forming voltage is applied, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. After the thermal step, if the memory cell passes verification, the next forming voltage is not applied to the memory cell. In addition, after one reset voltage is applied, if the memory cell passes verification, the next reset voltage is not applied to the memory cell.Type: ApplicationFiled: November 6, 2018Publication date: July 18, 2019Applicant: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Shao-Ching Liao, Yu-Ting Chen, Ming-Che Lin, Chien-Min Wu, Chia-Hua Ho
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Publication number: 20190213468Abstract: A synapse system is provided which includes three transistors and a resistance-switching element arranged between two neurons. The resistance-switching element has a resistance value and it is arranged between two neurons. A first transistor is connected between the resistance-switching element and one of the neurons. A second transistor and a third transistor are arranged between the two neurons, and are connected in series which interconnects with the gate of the first transistor. A first input signal is transmitted from one of the neurons to the other neuron through the first transistor. A second input signal is transmitted from one of the neurons to the other neuron through the second transistor and the third transistor. The resistance value of the resistance-switching element is changed based on the time difference between the first input signal and the second input signal.Type: ApplicationFiled: January 11, 2018Publication date: July 11, 2019Inventors: Frederick CHEN, Ping-Kun WANG, Shao-Ching LIAO, Chih-Cheng FU, Ming-Che LIN, Yu-Ting CHEN, Seow-Fong (Dennis) LIM
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Publication number: 20190214556Abstract: A method of forming a one-time-programmable resistive random access memory bit includes forming a resistive switching layer on a bottom electrode layer. The method also includes forming a top electrode layer on the resistive switching layer. The method also includes applying a forming voltage to the resistive switching layer, such that the electric potential of the top electrode layer is lower than that of the bottom electrode layer. The method also includes performing a bake process on the resistive switching layer. The vacancies in the resistive switching layer are randomly distributed.Type: ApplicationFiled: January 10, 2018Publication date: July 11, 2019Inventors: Frederick CHEN, Ping-Kun WANG, Chih-Cheng FU, Chien-Min WU, Shao-Ching LIAO
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Publication number: 20190035459Abstract: A forming method of a resistive memory device is provided. The forming method includes: conducting a forming procedure to apply a forming voltage to the resistive memory device such that the resistive memory device changes from a high resistive state to a low resistive state and measuring a first current of the resistive memory device; performing a thermal step on the resistive memory device and measuring a second current of the resistive memory device; and comparing the second current to the first current and determining to apply a first voltage signal or a second voltage signal to the resistive memory device or to finish the forming procedure according to a comparison result of the first current and the second current. In addition, a memory storage apparatus including a resistive memory device is also provided.Type: ApplicationFiled: July 26, 2018Publication date: January 31, 2019Applicant: Winbond Electronics Corp.Inventors: Shao-Ching Liao, Ping-Kun Wang, Ming-Che Lin, Min-Chih Wei, Chia-Hua Ho, Chien-Min Wu
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Publication number: 20190006007Abstract: A resistive memory apparatus and a setting method for a resistive memory cell thereof are provided. The setting method includes: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is finished; determining whether to perform a first resetting operation on the resistive memory cell according to a verifying result of the first verifying operation, and performing a second verifying operation on the resistive memory cell after the first resetting operation is determined to be performed and is finished; and determining whether to perform a second resetting operation on the resistive memory cell according to a verifying result of the second verifying operation, and performing a third verifying operation on the resistive memory cell after the second resetting operation is determined to be performed and is finished.Type: ApplicationFiled: October 11, 2017Publication date: January 3, 2019Applicant: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Shao-Ching Liao, Ming-Che Lin, Min-Chih Wei, Chia-Hua Ho, Chien-Min Wu
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Patent number: 10170184Abstract: A resistive memory apparatus and a setting method for a resistive memory cell thereof are provided. The setting method includes: performing a first setting operation on the resistive memory cell, and performing a first verifying operation on the resistive memory cell after the first setting operation is finished; determining whether to perform a first resetting operation on the resistive memory cell according to a verifying result of the first verifying operation, and performing a second verifying operation on the resistive memory cell after the first resetting operation is determined to be performed and is finished; and determining whether to perform a second resetting operation on the resistive memory cell according to a verifying result of the second verifying operation, and performing a third verifying operation on the resistive memory cell after the second resetting operation is determined to be performed and is finished.Type: GrantFiled: October 11, 2017Date of Patent: January 1, 2019Assignee: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Shao-Ching Liao, Ming-Che Lin, Min-Chih Wei, Chia-Hua Ho, Chien-Min Wu
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Publication number: 20180366197Abstract: A resistive memory and a resistance window recovery method for a resistive memory cell thereof are provided. During a first period, an over reset voltage difference is applied between a top electrode and a bottom electrode of the resistive memory cell, wherein the over reset voltage difference falls in a reset complementary switching (reset-CS) voltage range of the resistive memory cell. During a second period, a set voltage difference is applied between the top electrode and the bottom electrode of the resistive memory cell to increase a compliance current of the resistive memory cell. During a third period, a reset operation is performed on the resistive memory cell.Type: ApplicationFiled: June 5, 2018Publication date: December 20, 2018Applicant: Winbond Electronics Corp.Inventors: Ping-Kun Wang, Shao-Ching Liao, Ming-Che Lin, Min-Chih Wei, Chuan-Sheng Chou
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Patent number: 10157962Abstract: A resistive random access memory is provided. The resistive memory cell includes a substrate, a transistor on the substrate, a bottom electrode on the substrate and electrically connected to the transistor source/drain, several top electrodes on the bottom electrode, several resistance-switching layers between the top and bottom electrode, and several current limiting layers between the resistance-switching layer and top electrodes. The cell could improve the difficulty on recognizing 1/0 signal by current at high temperature environment and save the area on the substrate by generating several conductive filaments at one transistor location.Type: GrantFiled: June 1, 2015Date of Patent: December 18, 2018Assignee: Winbond Electronics Corp.Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao
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Patent number: 10079067Abstract: A data read method and a non-volatile memory apparatus using the same are provided. The data read method includes: obtaining a first read current and a second read current from a memory cell pair of the non-volatile memory; performing a calculation operation according to the first read current and the second read current to obtain a calculation result; and determining a logical state of the memory cell pair according to the calculation result. The calculation operation includes at least a signal addition operation and a signal multiplying operation.Type: GrantFiled: September 7, 2017Date of Patent: September 18, 2018Assignee: Winbond Electronics Corp.Inventors: Frederick Chen, Shao-Ching Liao, Ping-Kun Wang, Chia-Hua Ho
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Publication number: 20180233665Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode over a substrate, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer containing metal or semiconductor is disposed at sidewalls of the resistance-switching layer, and the sidewalls of the resistance-switching layer is doped with the metal or semiconductor from the sidewall protective layer.Type: ApplicationFiled: April 10, 2018Publication date: August 16, 2018Applicant: Winbond Electronics Corp.Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Po-Yen Hsu, Yi-Hsiu Chen, Ting-Ying Shen, Bo-Lun Wu, Meng-Hung Lin, Chia-Hua Ho, Ming-Che Lin
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Patent number: 9972779Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.Type: GrantFiled: December 14, 2015Date of Patent: May 15, 2018Assignee: Winbond Electronics Corp.Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Po-Yen Hsu, Yi-Hsiu Chen, Ting-Ying Shen, Bo-Lun Wu, Meng-Hung Lin
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Patent number: 9824733Abstract: An operating method for a resistive memory cell and a resistive memory are provided. The operating method for the resistive memory cell includes following steps. A forming operation for the resistive memory cell is performed. Whether the resistive memory cell is in a first state is determined, wherein the first state is corresponding to a first operation. When the resistive memory cell is not in the first state, a complementary switching operation regarding a second operation for the resistive memory cell is performed, so that the resistive memory cell generates a complementary switching phenomenon regarding the second operation. Thus, the resistive memory cell which cannot retain data by normal forming operation can effectively obtain the data retention capability by the complementary switching phenomenon.Type: GrantFiled: October 21, 2015Date of Patent: November 21, 2017Assignee: Winbond Electronics Corp.Inventors: Shao-Ching Liao, Ping-Kun Wang, Frederick Chen
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Publication number: 20170170394Abstract: A resistive random access memory is provided. The resistive random access memory includes a bottom electrode, a top electrode, a resistance-switching layer, an oxygen exchange layer, and a sidewall protective layer. The bottom electrode is disposed over a substrate. The top electrode is disposed over the bottom electrode. The resistance-switching layer is disposed between the bottom electrode and the top electrode. The oxygen exchange layer is disposed between the resistance-switching layer and the top electrode. The sidewall protective layer as an oxygen supply layer is at least disposed at sidewalls of the oxygen exchange layer.Type: ApplicationFiled: December 14, 2015Publication date: June 15, 2017Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Po-Yen Hsu, Yi-Hsiu Chen, Ting-Ying Shen, Bo-Lun Wu, Meng-Hung Lin
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Publication number: 20170117464Abstract: A resistive random access memory device is provided, which includes a bottom electrode, a resistive switching layer disposed on the bottom electrode, an oxidizable layer disposed on the resistive switching layer, a first oxygen diffusion barrier layer disposed between the oxidizable layer and the resistive switching layer, and a second oxygen diffusion barrier layer disposed on the oxidizable layer.Type: ApplicationFiled: October 22, 2015Publication date: April 27, 2017Inventors: Frederick CHEN, Shao-Ching LIAO, Ping-Kun WANG
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Publication number: 20170117038Abstract: An operating method for a resistive memory cell and a resistive memory are provided. The operating method for the resistive memory cell includes following steps. A forming operation for the resistive memory cell is performed. Whether the resistive memory cell is in a first state is determined, wherein the first state is corresponding to a first operation. When the resistive memory cell is not in the first state, a complementary switching operation regarding a second operation for the resistive memory cell is performed, so that the resistive memory cell generates a complementary switching phenomenon regarding the second operation. Thus, the resistive memory cell which cannot retain data by normal forming operation can effectively obtain the data retention capability by the complementary switching phenomenon.Type: ApplicationFiled: October 21, 2015Publication date: April 27, 2017Inventors: Shao-Ching Liao, Ping-Kun Wang, Frederick Chen
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Publication number: 20160351623Abstract: A resistive random access memory is provided. The resistive memory cell includes a substrate, a transistor on the substrate, a bottom electrode on the substrate and electrically connected to the transistor source/drain, several top electrodes on the bottom electrode, several resistance-switching layers between the top and bottom electrode, and several current limiting layers between the resistance-switching layer and top electrodes. The cell could improve the difficulty on recognizing 1/0 signal by current at high temperature environment and save the area on the substrate by generating several conductive filaments at one transistor location.Type: ApplicationFiled: June 1, 2015Publication date: December 1, 2016Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao
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Patent number: 9496036Abstract: A writing method for a resistive memory cell and a resistive memory are provided. The writing method includes following steps. A reference voltage is provided to a bit line of the resistive memory cell. A first voltage is provided to a word line of the resistive memory cell, and a second voltage is provided to a source line of the resistive memory cell, wherein the first voltage is not increased while the second voltage is progressively increased. Thus, when the writing method for the resistive memory cell is performed, the voltage of the word line is not increased while the voltage of the source line is progressively increased, so as to expand voltage window for reset operation. And, the chance for occurring the complementary switching manifestation of the resistive memory cell due to excessive input voltages is reduced.Type: GrantFiled: November 30, 2015Date of Patent: November 15, 2016Assignee: Winbond Electronics Corp.Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Pei-Hsiang Liao
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Publication number: 20160315255Abstract: A resistive random access memory (RRAM) including a first electrode, a second electrode, and a variable-resistance oxide layer disposed between the first electrode and the second electrode is provided. The RRAM further includes an oxygen exchange layer, an oxygen-rich layer, and a first oxygen barrier layer. The oxygen exchange layer is disposed between the variable-resistance oxide layer and the second electrode. The oxygen-rich layer is disposed between the oxygen exchange layer and the second electrode. The first oxygen barrier layer is disposed between the oxygen exchange layer and the oxygen-rich layer.Type: ApplicationFiled: March 11, 2016Publication date: October 27, 2016Inventors: Frederick Chen, Ping-Kun Wang, Shao-Ching Liao, Meng-Hung Lin
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Patent number: 9443587Abstract: A resistive memory apparatus and a writing method thereof are provided. In the method, logic data is received, and a corresponding resistive memory cell is selected. A logic level of the logic data is determined. When the logic data is in a first logic level, where a first reading current of the corresponding resistive memory cell is greater than a first reference current, a set pulse and a reset pulse are provided to the resistive memory cell during a writing period. When the logic data is in a second logic level, where a second reading current of the resistive memory cell is smaller than a second reference current, the reset pulse is provided to the resistive memory cell during the writing period. Polarities of the reset pulse and the set pulse are opposite.Type: GrantFiled: July 21, 2015Date of Patent: September 13, 2016Assignee: Winbond Electronics Corp.Inventors: Frederick Chen, Meng-Hung Lin, Ping-Kun Wang, Shao-Ching Liao, Chuan-Sheng Chou