Abstract: Graphene layers made of primarily sp2 bonded atoms and associated methods are disclosed. In one aspect, for example, a method of forming a graphite film can include heating a solid substrate under vacuum to a solubilizing temperature that is less than a melting point of the solid substrate, solubilizing carbon atoms from a graphite source into the heated solid substrate, and cooling the heated solid substrate at a rate sufficient to form a graphite film from the solubilized carbon atoms on at least one surface of the solid substrate. The graphite film is formed to be substantially free of lattice defects.

Abstract: Graphene layers made of primarily sp2 bonded atoms and associated methods are disclosed. In one aspect, for example, a method of forming a graphite film can include heating a solid substrate under vacuum to a solubilizing temperature that is less than a melting point of the solid substrate, solubilizing carbon atoms from a graphite source into the heated solid substrate, and cooling the heated solid substrate at a rate sufficient to form a graphite film from the solubilized carbon atoms on at least one surface of the solid substrate. The graphite film is formed to be substantially free of lattice defects.

Abstract: A microelectronic 3D packaging structure and a method of manufacturing the same are introduced. The microelectronic 3D packaging structure includes a first board with a plurality of a first edges and disposed with a first electronic device; a second board with a plurality of a second edges and disposed with a second electronic device, wherein at least one second edge of the second board is jointed to at least one first edge of the first board to form a joint line; and a joint connection portion disposed at the joint line of the two adjacent boards and adapted to function as a connection path for transmitting signals.

Abstract: A microelectronic 3D packaging structure and a method of manufacturing the same are introduced. The microelectronic 3D packaging structure includes a first board with a plurality of a first edges and disposed with a first electronic device; a second board with a plurality of a second edges and disposed with a second electronic device, wherein at least one second edge of the second board is jointed to at least one first edge of the first board to form a joint line; and a joint connection portion disposed at the joint line of the two adjacent boards and adapted to function as a connection path for transmitting signals.

Abstract: A vision based pedestrian and cyclist detection method includes receiving an input image, calculating a pixel value difference between each pixel and the neighbor pixels thereof, quantifying the pixel value difference as a weight of pixel, proceeding statistics for the pixel value differences and the weights, determining intersections of the statistics as a feature of the input image, classifying the feature into human feature and non-human feature, confirming the human feature belonging to cyclist according to the spatial relationship between the human feature and the detected two-wheeled vehicle, and retaining one detection result for each cyclist by suppressing other weaker spatial relationships between the human feature and the detected two-wheeled vehicle.

Abstract: A vision based pedestrian and cyclist detection method includes receiving an input image, calculating a pixel value difference between each pixel and the neighbor pixels thereof, quantifying the pixel value difference as a weight of pixel, proceeding statistics for the pixel value differences and the weights, determining intersections of the statistics as a feature of the input image, classifying the feature into human feature and non-human feature, confirming the human feature belonging to cyclist according to the spatial relationship between the human feature and the detected two-wheeled vehicle, and retaining one detection result for each cyclist by suppressing other weaker spatial relationships between the human feature and the detected two-wheeled vehicle.

Abstract: A multi-channel glare-suppression device of a digital image system first acquires a spatial image, and at least one first lens set then collects light from the spatial image and generates an optical image. The optical image then passes through or is reflected by an optical modulation module to generate a modulated image. At least one second lens set further scales the modulated image and focuses the modulated image to generate a scaled image on a photo-sensing module for the photo-sensing module to convert the scaled image into an image signal. A processing module senses the photo-sensing module. When detecting a current higher than a threshold generated in a region of the photo-sensing module, the processing module then generates the control signal to modulate a region of the modulated image so as to attenuate the glare in the region of the modulated image.

Abstract: Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C.

Abstract: Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C.

Abstract: A thermal conduction device and a method for fabricating the same are disclosed. Firstly, arrange a plurality of diamond particles on a plane according to a predetermined pattern to form a diamond particle monolayer. Next, apply a forming process on a metal material such that the metal material forms a metal matrix wrapping the diamond particles to form a composite body including the diamond particle monolayer embedded in the metal matrix. Next, stack a plurality of the composite bodies and perform a heating process to join the metal matrixes to each other to form the thermal conduction device. The device is characterized in arranging diamond particles on a plane to form a two-dimensional monolayer structure and manufactured via assembling the two-dimensional monolayer structures to form a three-dimensional multilayer structure. By controlling the arrangement of the diamond particles, the thermal conduction device can have superior thermal conduction performance.

Abstract: Stress regulated semiconductor devices and associated methods are provided. In one aspect, for example, a stress regulated semiconductor device can include a semiconductor layer, a stress regulating interface layer including a carbon layer formed on the semiconductor layer, and a heat spreader coupled to the carbon layer opposite the semiconductor layer. The stress regulating interface layer is operable to reduce the coefficient of thermal expansion difference between the semiconductor layer and the heat spreader to less than or equal to about 10 ppm/° C.

Abstract: A thermal conduction device and a method for fabricating the same are disclosed. Firstly, arrange a plurality of diamond particles on a plane according to a predetermined pattern to form a diamond particle monolayer. Next, apply a forming process on a metal material such that the metal material forms a metal matrix wrapping the diamond particles to form a composite body including the diamond particle monolayer embedded in the metal matrix. Next, stack a plurality of the composite bodies and perform a heating process to join the metal matrixes to each other to form the thermal conduction device. The device is characterized in arranging diamond particles on a plane to form a two-dimensional monolayer structure and manufactured via assembling the two-dimensional monolayer structures to form a three-dimensional multilayer structure. By controlling the arrangement of the diamond particles, the thermal conduction device can have superior thermal conduction performance.

Abstract: The present invention relates to a method for manufacturing a substrate, including: providing a metal base; forming an oxide layer on one surface of the metal base; forming a chemical barrier layer on the oxide layer; forming an intermediate layer on the chemical barrier layer; forming a first metal layer on the intermediate layer; and removing parts of the intermediate layer and the first metal layer by etching to form a first metal wiring layer. Moreover, the present invention may include the following steps alternatively: laminating an insulating adhesive layer and a second metal layer on an exposed area of the chemical barrier layer; forming a second metal wiring layer by etching a part of the second metal layer; forming a surface metal layer; and forming a chip layer on the surface metal layer. The present invention also provides a structure of a substrate obtained according to the aforementioned method.

Abstract: Electrically insulating layers having increased thermal conductivity, as well as associated devices and methods are disclosed. In one aspect, for example, a printed circuit board is provided including a substrate and an electrically insulating layer coated on at least one surface of the substrate, the electrically insulating layer including a plurality of hBN particles bound in a binder material.

Abstract: Electrical substrates having low current leakage and high thermal conductivity, including associated methods, are provided. In one aspect for example, a multilayer substrate having improved thermal conductivity and dielectric properties can include a metal layer having a working surface with a local Ra of greater than about 0.1 micron, a dielectric layer coated on the working surface of the metal layer, and a thermally conductive insulating layer disposed on the dielectric layer, wherein the multilayer substrate has a minimum resistivity between the metal layer and the thermally conductive insulating layer across all of the working surface of at least 1×106 ohms.

Abstract: A highly thermal conductive circuit board includes a composite substrate, and a metal layer, an insulating layer, and a conductor layer sequentially disposed on the composite substrate. When at least one electronic element is electrically disposed on the conductor layer of the highly thermal conductive circuit board, heat produced by the electronic element in operation is rapidly dissipated through characteristics such as a high thermal conductivity and a low thermal expansion coefficient of the highly thermal conductive circuit board.

Abstract: The present invention relates a packaging carrier with high heat dissipation for packaging a chip, comprising: a carrier body, an interfacial metal layer, at least one diamond-like carbon thin film, a plated layer, and an electrode layer. Herein, the packaging carrier further comprises through holes. The present invention further discloses a method for manufacturing the aforementioned packaging carrier, comprising: providing a carrier body; forming an interfacial metal layer on the upper surface of the carrier body; forming a diamond-like carbon thin film on the interfacial metal layer; forming a plated layer on the diamond-like carbon thin film; forming an electrode layer on the lower surface of the carrier body; and forming through holes extending through all or part of the aforementioned elements. The present invention uses a diamond-like carbon thin film and through holes for heat dissipation in three dimensions to improve heat dissipation of an electronic device.

Abstract: Graphene layers made of primarily sp2 bonded atoms and associated methods are disclosed. In one aspect, for example, a method of forming a graphite film can include heating a solid substrate under vacuum to a solubilizing temperature that is less than a melting point of the solid substrate, solubilizing carbon atoms from a graphite source into the heated solid substrate, and cooling the heated solid substrate at a rate sufficient to form a graphite film from the solubilized carbon atoms on at least one surface of the solid substrate. The graphite film is formed to be substantially free of lattice defects.

Abstract: Method for production of diamond-like carbon film having semiconducting properties comprises preparing a boron-doped diamond-like carbon (B-DLC) thin film on a silicon substrate through a radio frequency magnetron sputtering process, wherein a composite target material formed by inserting boron tablet as a dopant source in a graphite target is used. After forming a boron-containing diamond-like carbon film, the thin film is annealed at a temperature of 500° C. and kept at this temperature for 10 minutes, and determine its carrier concentration and resistivity. Thus demonstrated that the polarity of said boron-doped diamond-like carbon film is p-type semiconductor characteristic. Carrier concentration can be up to 1.3×1018 cm-3, and its resistivity is about 0.6 ?-cm; consequently.

Abstract: A circuit board having high thermal conductivity comprises a substrate, a plurality of thermal conductive insulating layers, a patterned electrical conductive layer, a plurality of through-holes and a soldering layer. The substrate has an upper surface and a lower surface; the thermal conductive insulating layers are respectively formed on the upper surface and the lower surface of the substrate. The patterned electrical conductive layer is disposed on the surfaces of the thermal conductive insulating layers. The plurality of through-holes are extended through the substrate and electrically connected to the patterned electrical conductive layer, and the soldering layer is partially formed on the patterned electric conductive layer. The present invention also discloses a method for manufacturing the circuit board as above-mentioned.