Patents by Inventor Shao-fu Sanford Chu
Shao-fu Sanford Chu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11721609Abstract: In a method for forming an integrated structure, a top dielectric layer is formed over a top surface of a substrate. The top dielectric layer includes a plurality of vias that are formed through the top dielectric layer and extend into the substrate. A bottom dielectric layer is formed on a bottom surface of the substrate. An isolation opening and a plurality of contact openings are further formed in the bottom dielectric layer and the substrate, where the isolation opening passes through the bottom dielectric layer and extends from the bottom surface to the top surface of the substrate. The isolation opening is filled with an insulating layer to form an isolation trench. The plurality of contact openings are filled with a conductive layer to form a plurality of through silicon contacts (TSCs). A conductive plate is further formed over the bottom dielectric layer.Type: GrantFiled: June 14, 2021Date of Patent: August 8, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Liang Chen, Wei Liu, Shao-Fu Sanford Chu
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Patent number: 11710679Abstract: In a TSC structure, a first dielectric layer is formed over a first main surface of a substrate. A TSC is formed in the first dielectric layer and the substrate so that the TSC passes through the first dielectric layer and extends into the substrate. A conductive plate is formed over the first dielectric layer and electrically coupled with the TSC. A second dielectric layer is formed on an opposing second main surface of the substrate. A first via is formed in the second dielectric layer, and a first end of the first via extends into the substrate to be in contact with the TSC. A second via is formed in the second dielectric layer and a first end of the second via extends into the substrate. A metal line is formed over the second dielectric layer so as to be coupled to the first via and the second via.Type: GrantFiled: June 3, 2021Date of Patent: July 25, 2023Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Liang Chen, Wei Liu, Shao-Fu Sanford Chu
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Publication number: 20210313251Abstract: In a method for forming an integrated structure, a top dielectric layer is formed over a top surface of a substrate. The top dielectric layer includes a plurality of vias that are formed through the top dielectric layer and extend into the substrate. A bottom dielectric layer is formed on a bottom surface of the substrate. An isolation opening and a plurality of contact openings are further formed in the bottom dielectric layer and the substrate, where the isolation opening passes through the bottom dielectric layer and extends from the bottom surface to the top surface of the substrate. The isolation opening is filled with an insulating layer to form an isolation trench. The plurality of contact openings are filled with a conductive layer to form a plurality of through silicon contacts (TSCs). A conductive plate is further formed over the bottom dielectric layer.Type: ApplicationFiled: June 14, 2021Publication date: October 7, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Liang CHEN, Wei LIU, Shao-Fu Sanford CHU
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Publication number: 20210296210Abstract: In a TSC structure, a first dielectric layer is formed over a first main surface of a substrate. A TSC is formed in the first dielectric layer and the substrate so that the TSC passes through the first dielectric layer and extends into the substrate. A conductive plate is formed over the first dielectric layer and electrically coupled with the TSC. A second dielectric layer is formed on an opposing second main surface of the substrate. A first via is formed in the second dielectric layer, and a first end of the first via extends into the substrate to be in contact with the TSC. A second via is formed in the second dielectric layer and a first end of the second via extends into the substrate. A metal line is formed over the second dielectric layer so as to be coupled to the first via and the second via.Type: ApplicationFiled: June 3, 2021Publication date: September 23, 2021Applicant: Yangtze Memory Technologies Co., Ltd.Inventors: Liang CHEN, Wei LIU, Shao-Fu Sanford CHU
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Patent number: 11069596Abstract: In a TSC structure, a first dielectric layer is formed over a first main surface of a substrate. The substrate includes an opposing second main surface. A TSC is formed in the first dielectric layer and the substrate so that the TSC passes through the first dielectric layer and extends into the substrate. A conductive plate is formed over the first dielectric layer and electrically coupled with the TSC. An isolation trench is formed in the substrate to surround the conductive plate and spaced apart from the conductive plate. A second dielectric layer is formed on the second main surface of the substrate. A first plurality of vias are formed in the second dielectric layer that extend into the substrate and are connected to the TSC. A second plurality of vias are formed in the second dielectric layer that extend into the substrate and are not connected to the TSC.Type: GrantFiled: March 27, 2019Date of Patent: July 20, 2021Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Liang Chen, Wei Liu, Shao-Fu Sanford Chu
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Patent number: 10847534Abstract: Embodiments of staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed above the substrate and including conductor/dielectric layer pairs stacked alternatingly, and an array of memory strings each extending vertically through an inner region of the memory stack. An outer region of the memory stack includes a first staircase structure disposed on the substrate and a second staircase structure disposed above the first staircase structure. First edges of the conductor/dielectric layer pairs in the first staircase structure along a vertical direction away from the substrate are staggered laterally away from the array of memory strings. Second edges of the conductor/dielectric layer pairs in the second staircase structure along the vertical direction away from the substrate are staggered laterally toward the array of memory strings.Type: GrantFiled: September 22, 2018Date of Patent: November 24, 2020Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Shao-Fu Sanford Chu
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Publication number: 20200266128Abstract: In a TSC structure, a first dielectric layer is formed over a first main surface of a substrate. The substrate includes an opposing second main surface. A TSC is formed in the first dielectric layer and the substrate so that the TSC passes through the first dielectric layer and extends into the substrate. A conductive plate is formed over the first dielectric layer and electrically coupled with the TSC. An isolation trench is formed in the substrate to surround the conductive plate and spaced apart from the conductive plate. A second dielectric layer is formed on the second main surface of the substrate. A first plurality of vias are formed in the second dielectric layer that extend into the substrate and are connected to the TSC. A second plurality of vias are formed in the second dielectric layer that extend into the substrate and are not connected to the TSC.Type: ApplicationFiled: March 27, 2019Publication date: August 20, 2020Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventors: Liang CHEN, Wei Liu, Shao-Fu Sanford Chu
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Publication number: 20200006377Abstract: Embodiments of staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed above the substrate and including conductor/dielectric layer pairs stacked alternatingly, and an array of memory strings each extending vertically through an inner region of the memory stack. An outer region of the memory stack includes a first staircase structure disposed on the substrate and a second staircase structure disposed above the first staircase structure. First edges of the conductor/dielectric layer pairs in the first staircase structure along a vertical direction away from the substrate are staggered laterally away from the array of memory strings. Second edges of the conductor/dielectric layer pairs in the second staircase structure along the vertical direction away from the substrate are staggered laterally toward the array of memory strings.Type: ApplicationFiled: September 22, 2018Publication date: January 2, 2020Inventor: Shao-Fu Sanford Chu
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Patent number: 9466661Abstract: Methods for fabricating MIM capacitors with low VCC or decoupling and analog/RF capacitors on a single chip and the resulting devices are provided. Embodiments include forming: first and second metal lines in a substrate; a first electrode over, but insulated from, the first metal line; a first high-k dielectric layer on the first electrode, the first high-k dielectric layer having a coefficient ?; a second electrode on the first high-k dielectric layer and over a portion of the first electrode; a second high-k dielectric layer on the second electrode, the second high-k dielectric layer having a coefficient ?? opposite in polarity but substantially equal in magnitude to ?; a third electrode on the second high-k dielectric layer over the entire first electrode; and a metal-filled via through a dielectric layer down to the first metal line, and a metal-filled via through the dielectric layer down to the second metal line.Type: GrantFiled: October 10, 2014Date of Patent: October 11, 2016Assignee: GLOBALFOUNDRIES INC.Inventors: Dina Triyoso, Shao-Fu Sanford Chu, Bo Yu
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Publication number: 20160104762Abstract: Methods for fabricating MIM capacitors with low VCC or decoupling and analog/RF capacitors on a single chip and the resulting devices are provided. Embodiments include forming: first and second metal lines in a substrate; a first electrode over, but insulated from, the first metal line; a first high-k dielectric layer on the first electrode, the first high-k dielectric layer having a coefficient ?; a second electrode on the first high-k dielectric layer and over a portion of the first electrode; a second high-k dielectric layer on the second electrode, the second high-k dielectric layer having a coefficient ?? opposite in polarity but substantially equal in magnitude to ?; a third electrode on the second high-k dielectric layer over the entire first electrode; and a metal-filled via through a dielectric layer down to the first metal line, and a metal-filled via through the dielectric layer down to the second metal line.Type: ApplicationFiled: October 10, 2014Publication date: April 14, 2016Inventors: Dina TRIYOSO, Shao-Fu Sanford CHU, Bo YU
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Patent number: 9269770Abstract: An integrated circuit system includes a substrate, forming a gate over the substrate, forming a first drift region having a first counter diffused region and a source diffused region, the first drift region in the substrate adjacent a first side of the gate, and forming a second drift region having a second counter diffused region and a drain diffused region, the second drift region in the substrate adjacent a second side of the gate opposite the first side of the gate.Type: GrantFiled: March 8, 2007Date of Patent: February 23, 2016Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Yisuo Li, Gang Chen, Francis Benistant, Purakh Raj Verma, Hong Yang, Shao-fu Sanford Chu
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Patent number: 8536016Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor.Type: GrantFiled: September 19, 2011Date of Patent: September 17, 2013Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shao-fu Sanford Chu, Shaoqiang Zhang, Johnny Kok Wai Chew
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Patent number: 8138051Abstract: A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor.Type: GrantFiled: June 19, 2009Date of Patent: March 20, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Yemin Dong, Purakh Raj Verma, Xin Zou, Chao Cheng, Shao-fu Sanford Chu
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Patent number: 8115276Abstract: An integrated circuit system that includes: providing a substrate including front-end-of-line circuitry; forming a first metallization layer over the substrate and electrically connected to the substrate; forming a viabar or a via group over the first metallization layer; and forming a second metallization layer over the first metallization layer and electrically connected to the first metallization layer through either the viabar or the via group.Type: GrantFiled: June 3, 2008Date of Patent: February 14, 2012Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shaoqing Zhang, Fan Zhang, Shao-fu Sanford Chu, Bei Chao Zhang
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Publication number: 20120007214Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers, including interconnecting a first cluster adjacent to a second cluster, to form a capacitor.Type: ApplicationFiled: September 19, 2011Publication date: January 12, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Shao-fu Sanford Chu, Shaoqiang Zhang, Johnny Kok Wai Chew
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Patent number: 8021954Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.Type: GrantFiled: May 22, 2009Date of Patent: September 20, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Shao-fu Sanford Chu, Shaoqing Zhang, Johnny Kok Wai Chew, Chit Hwei Ng
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Patent number: 7951680Abstract: A method for manufacturing an integrated circuit system that includes: providing a substrate including an active device; forming a drift region in the substrate, the drift region bounded in part by a top surface of the substrate and spaced apart from a source; and forming a drain above the drift region.Type: GrantFiled: October 30, 2008Date of Patent: May 31, 2011Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Guowei Zhang, Yisuo Li, Ming Li, Purakh Raj Verma, Shao-fu Sanford Chu
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Publication number: 20100320529Abstract: A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor.Type: ApplicationFiled: June 19, 2009Publication date: December 23, 2010Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.Inventors: Yemin Dong, Purakh Raj Verma, Xin Zou, Chao Cheng, Shao-fu Sanford Chu
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Publication number: 20100295153Abstract: A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.Type: ApplicationFiled: May 22, 2009Publication date: November 25, 2010Applicant: Chartered Semiconductor Manufacturing Ltd.Inventors: Shao-fu Sanford Chu, Shaoqing Zhang, Johnny Kok Wai Chew, Chit Hwei Ng
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Patent number: 7721414Abstract: A method of manufacturing a 3-D spiral stacked inductor is provided having a substrate with a plurality of turns in a plurality of levels wherein the number of levels increases from an inner turn to the outer turn of the inductor. First and second connecting portions are respectively connected to an inner turn and an outermost turn, and a dielectric material contains the first and second connecting portions and the plurality of turns over the substrate.Type: GrantFiled: October 8, 2004Date of Patent: May 25, 2010Assignee: Chartered Semiconductor Manufacturing Ltd.Inventors: Choon-Beng Sia, Kiat Seng Yeo, Shao-fu Sanford Chu, Cheng Yeow Ng, Kok Wai Chew, Wang Ling Goh