Patents by Inventor Shao-Heng CHOU

Shao-Heng CHOU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9922162
    Abstract: A method includes generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions includes a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a first spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the first spacing values.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: March 20, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming Ho, C. Y. (Chia-Yi) Chen, Hsiu-Wen Hsueh, Jun-Fu Huang, Shao-Heng Chou
  • Publication number: 20160103948
    Abstract: A method includes generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions includes a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a first spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the first spacing values.
    Type: Application
    Filed: December 21, 2015
    Publication date: April 14, 2016
    Inventors: Chia-Ming HO, C. Y. (Chia-Yi) CHEN, Hsiu-Wen HSUEH, Jun-Fu HUANG, Shao-Heng CHOU
  • Patent number: 9218448
    Abstract: A method comprises generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions comprises a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the spacing values.
    Type: Grant
    Filed: January 20, 2014
    Date of Patent: December 22, 2015
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming Ho, C. Y. Chen, Hsiu-Wen Hsueh, Jun-Fu Huang, Shao-Heng Chou
  • Publication number: 20150205905
    Abstract: A method comprises generating a plurality of multiple patterning decompositions associated with a layout of an integrated circuit. Each of the plurality of multiple patterning decompositions comprises a first pattern associated with a first mask, a second pattern associated with a second mask, the first mask and the second mask being two masks of a multiple patterning mask set, a width value associated with at least one of the first pattern or the second pattern, and a spacing value between the first pattern and the second pattern. A file is generated comprising a plurality of dielectric constant values associated with the plurality of multiple patterning decompositions that are based on the width values and the spacing values.
    Type: Application
    Filed: January 20, 2014
    Publication date: July 23, 2015
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Ming HO, C, Y. CHEN, Hsiu-Wen HSUEH, Jun-Fu HUANG, Shao-Heng CHOU