Patents by Inventor Shao-Huan Wang

Shao-Huan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210004517
    Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.
    Type: Application
    Filed: September 23, 2020
    Publication date: January 7, 2021
    Inventors: Shao-Huan WANG, Sheng-Hsiung CHEN, Wen-Hao CHEN, Chun-Chen CHEN, Hung-Chih OU
  • Patent number: 10868538
    Abstract: A logic cell structure includes: a first portion, with a first height, arranged to be a first layout of a first semiconductor element; a second portion, with the first height, arranged to be a second layout of a second semiconductor element, wherein the first portion is separated from the second portion; and a third portion arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: December 15, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shao-Huan Wang, Chun-Chen Chen, Sheng-Hsiung Chen, Kuo-Nan Yang
  • Patent number: 10817643
    Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: October 27, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou
  • Publication number: 20200328202
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Application
    Filed: June 25, 2020
    Publication date: October 15, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung CHEN, Jerry Chang-Jui KAO, Fong-Yuan CHANG, Po-Hsiang HUANG, Shao-Huan WANG, XinYong WANG, Yi-Kan CHENG, Chun-Chen CHEN
  • Patent number: 10804200
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Publication number: 20200285798
    Abstract: A method of forming an integrated device includes: providing a first via pillar file specifying a first via pillar; providing a second via pillar file specifying a second via pillar; arranging, by a processor, the first via pillar to electrically connect to a circuit cell in a first circuit; arranging an interconnecting path for electrical connection of the first via pillar to another circuit cell; arranging, by the processor, the second via pillar to replace the first via pillar when the first via pillar induces an electromigration (EM) phenomenon; re-routing the interconnecting path with replacement of the first via pillar to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: CHUN-YAO KU, WEN-HAO CHEN, MING-TAO YU, SHAO-HUAN WANG, JYUN-HAO CHANG
  • Patent number: 10741539
    Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen
  • Patent number: 10678991
    Abstract: A method of forming an integrated device includes: pre-storing a plurality of via pillars in a storage tool; arranging a first via pillar selected from the plurality of via pillars to electrically connect to a circuit cell in a first circuit; analyzing electromigration (EM) information of the first circuit to determine if the first via pillar induces an EM phenomenon; arranging a second via pillar selected from the plurality of via pillars to replace the first via pillar of the circuit cell to generate a second circuit when the first via pillar induces the EM phenomenon; and generating the integrated device according to the second circuit.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 9, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Yao Ku, Wen-Hao Chen, Ming-Tao Yu, Shao-Huan Wang, Jyun-Hao Chang
  • Publication number: 20200097634
    Abstract: An integrated circuit includes a first bit flip-flop and a second flip-flop. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first flip-flop and the second flip-flop are part of a multibit flip-flop configured to share at least a first clock pin. The first clock pin is configured to receive the first clock signal.
    Type: Application
    Filed: September 3, 2019
    Publication date: March 26, 2020
    Inventors: Sheng-Hsiung CHEN, Shao-Huan WANG, Wen-Hao CHEN, Chun-Yao KU, Hung-Chih OU
  • Publication number: 20200089840
    Abstract: A method for outputting a first number of subsets of a layer pattern comprising a plurality of cells arranged in a row includes selecting subsets of cells from the plurality of cells, constructing a graph representation for each subset of cells, identifying graph representations that are not colorable with a first number of labels, identifying subsets of cells that correspond to the identified graph representations, changing a distance between cells in each of the identified subset of cells, wherein the changed distances are greater than the first spacing, labeling the graph representations with the first number of labels, and outputting subsets of the layer pattern to a machine readable storage medium for manufacturing a set of masks that is used to form a single, patterned layer. Each subset of the layer pattern represents a separate mask pattern and includes features of the layer pattern corresponding to a label in the labeled graph representations.
    Type: Application
    Filed: November 21, 2019
    Publication date: March 19, 2020
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Huan WANG, Sheng-Hsiung Chen, Fong-Yuan Chang, Po-Hsiang Huang
  • Publication number: 20200004917
    Abstract: A method of forming an integrated device includes: pre-storing a plurality of via pillars in a storage tool; arranging a first via pillar selected from the plurality of via pillars to electrically connect to a circuit cell in a first circuit; analyzing an electromigration information of the first circuit to determine if the first via pillar induces EM phenomenon; arranging a second via pillar selected from the plurality of via pillars to replace the first via pillar of the circuit cell to generate a second circuit when the first via pillar induces EM phenomenon; and generating the integrated device according to the second circuit.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 2, 2020
    Inventors: CHUN-YAO KU, WEN-HAO CHEN, MING-TAO YU, SHAO-HUAN WANG, JYUN-HAO CHANG
  • Patent number: 10521545
    Abstract: A method for outputting a first number of subsets of a layer pattern comprising a plurality of cells arranged in a row includes selecting subsets of cells from the plurality of cells, constructing a graph representation for each subset of cells, identifying graph representations that are not colorable with a first number of labels, identifying subsets of cells that correspond to the identified graph representations, changing a distance between cells in each of the identified subset of cells, wherein the changed distances are greater than the first spacing, labeling the graph representations with the first number of labels, and outputting subsets of the layer pattern to a machine readable storage medium for manufacturing a set of masks that is used to form a single, patterned layer. Each subset of the layer pattern represents a separate mask pattern and includes features of the layer pattern corresponding to a label in the labeled graph representations.
    Type: Grant
    Filed: April 15, 2016
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Fong-Yuan Chang, Po-Hsiang Huang
  • Patent number: 10509887
    Abstract: The present disclosure describes a method for detecting unacceptable connection patterns. The method includes, using a processor to perform at least one of: performing an automated place-and-route (APR) process on a circuit layout that includes a first standard cell without a marker layer to generate a circuit graphic database system (GDS) file from the circuit layout, generating a standard-cell GDS file that includes a second standard cell with at least one marker layer applied to the second standard cell, and merging the circuit GDS file with the standard-cell GDS file to generate a merged GDS file that includes the first standard cell with at least one marker layer based on the second standard cell. The method further includes determining whether a connection pattern of the first standard cell in the merged GDS file is an unacceptable connection pattern.
    Type: Grant
    Filed: February 28, 2018
    Date of Patent: December 17, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung Chen, Ming-Huei Tsai, Shao-Huan Wang, Shu-Yu Chen, Wen-Hao Chen, Chun-Chen Chen
  • Publication number: 20190322180
    Abstract: A power supply system with hydrogen fuel cell is provided, comprising a hydrogen fuel cell module converting hydrogen fuel into electrical power for outputting. A boost charging module electrically connected to the hydrogen fuel cell module receives, boosts and converts the electric power into charging power. At least two battery packs connected in parallel are electrically connected to the boost charging module and an external load respectively. When one of the battery packs discharges the external load, the other selectively receives charging power from the boost charging module. A control module electrically connected to the above controls the boost charging module to receive electrical power and convert it into charging power and controls the battery packs to alternate performing discharging the external load and charging from the boost charging module repeatedly by turns. The present invention combines hydrogen fuel cells to provide an innovative power supply system.
    Type: Application
    Filed: August 22, 2018
    Publication date: October 24, 2019
    Inventors: KAI-TAI SONG, SZ-SHENG WANG, SHAO-HUAN SONG
  • Publication number: 20190266309
    Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.
    Type: Application
    Filed: May 13, 2019
    Publication date: August 29, 2019
    Inventors: Shao-Huan WANG, Sheng-Hsiung CHEN, Wen-Hao CHEN, Chun-Chen CHEN, Hung-Chih OU
  • Patent number: 10396063
    Abstract: In some embodiments, a first cell layout and a second cell layout are provided and combined into a third cell layout. Each of the first cell layout and the second cell layout includes a higher power line, a lower power line, an output pin, at least one up transistor and at least one down transistor formed to electrically couple the output pin to the higher power line and the output pin to the lower power line, respectively. The at least one up transistor and the at least one down transistor of the second cell layout include a gate line. For the combining, the gate line is non-selectively electrically coupled to the output pin of the first cell layout to form a first node. A design layout in which the third cell layout is used at different locations is generated.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: August 27, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Fong-Yuan Chang, Lee-Chung Lu, Yi-Kan Cheng, Sheng-Hsiung Chen, Po-Hsiang Huang, Shun Li Chen, Jeo-Yen Lee, Jyun-Hao Chang, Shao-Huan Wang, Chien-Ying Chen
  • Publication number: 20190155983
    Abstract: The present disclosure describes a method for detecting unacceptable connection patterns. The method includes, using a processor to perform at least one of: performing an automated place-and-route (APR) process on a circuit layout that includes a first standard cell without a marker layer to generate a circuit graphic database system (GDS) file from the circuit layout, generating a standard-cell GDS file that includes a second standard cell with at least one marker layer applied to the second standard cell, and merging the circuit GDS file with the standard-cell GDS file to generate a merged GDS file that includes the first standard cell with at least one marker layer based on the second standard cell. The method further includes determining whether a connection pattern of the first standard cell in the merged GDS file is an unacceptable connection pattern.
    Type: Application
    Filed: February 28, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung CHEN, Ming-Huei Tsai, Shao-Huan Wang, Shu-Yu Chen, Wen-Hao Chen, Chun-Chen Chen
  • Patent number: 10289794
    Abstract: A system is includes a processor and a computer readable medium. The computer readable medium connected to the processor. The computer readable medium is configured to store instructions. The processor is configured to execute the instructions for determining, according to at least one parameter of a cell in a semiconductor device indicated by a design file, a layout pattern indicating a via pillar structure that meets an electromigration (EM) rule. The via pillar structure comprises metal layers and at least one via, and the at least one via is coupled to the metal layers. The processor is further configured to execute the instructions for including, in the design file, the layout pattern indicating the via pillar structure. The processor is further configured to execute the instructions for generating data which indicate the design file, for fabrication of the semiconductor device.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: May 14, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou
  • Publication number: 20190096805
    Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.
    Type: Application
    Filed: November 26, 2018
    Publication date: March 28, 2019
    Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
  • Publication number: 20190064770
    Abstract: Exemplary embodiments for multiple standard cell libraries are disclosed that include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations have similar functionality as their one or more standard cells but are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for analog circuitry and/or digital circuitry of an electronic device. In an exemplary embodiment, a semiconductor foundry and/or semiconductor technology node can impose one or more electronic design constraints on the placement of the one or more standard cells onto an electronic device design real estate.
    Type: Application
    Filed: November 1, 2017
    Publication date: February 28, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Sheng-Hsiung CHEN, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen