Patents by Inventor Shao-Huan Wang
Shao-Huan Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20240088899Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.Type: ApplicationFiled: November 24, 2023Publication date: March 14, 2024Inventors: SHAO-HUAN WANG, CHUN-CHEN CHEN, SHENG-HSIUNG CHEN, KUO-NAN YANG
-
Publication number: 20240020451Abstract: An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.Type: ApplicationFiled: July 28, 2023Publication date: January 18, 2024Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Hsiung Chen, Chun-Chen Chen, Shao-huan Wang, Kuo-Nan Yang, Chung-Hsing Wang, Ren-Zheng Liao, Meng-Xiang Lee
-
Patent number: 11855632Abstract: A logic cell structure includes a first portion, a second portion and a third portion. The first portion, arranged to be a first layout of a first semiconductor element, is placed in a first cell row of a substrate area extending in a first direction. The second portion, arranged to be a second layout of a second semiconductor element, is placed in a second cell row of the substrate area. The third portion is arranged to be a third layout of an interconnecting path used for coupling the first semiconductor element and the second semiconductor element. The first, second and third portions are bounded by a bounding box with a height in a second direction and a width in the first direction. Respective centers of the first portion and the second portion are arranged in a third direction different from each of the first direction and the second direction.Type: GrantFiled: December 8, 2020Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Shao-Huan Wang, Chun-Chen Chen, Sheng-Hsiung Chen, Kuo-Nan Yang
-
Publication number: 20230334219Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability, and includes a first reset pin configured to receive a first reset signal. The second flip-flop has a second driving capability different from the first driving capability. The second flip-flop includes a second reset pin configured to receive the first reset signal, and the first reset pin and the second reset pin are coupled together. The first inverter is configured to receive a first clock signal on a first clock pin, and configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.Type: ApplicationFiled: June 19, 2023Publication date: October 19, 2023Inventors: Sheng-Hsiung CHEN, Wen-Hao CHEN, Hung-Chih OU, Chun-Yao KU, Shao-Huan WANG
-
Patent number: 11748542Abstract: An integrated circuit layout is provided. The integrated circuit layout includes one or more first cell rows partially extending across a space arranged for an integrated circuit layout along a first direction. Each of the one or more first cell rows has a first height along a second direction perpendicular to the first direction. The integrated circuit layout includes one or more third cell rows partially extending across the space along the first direction. Each of the one or more third cell rows has a second height along the second direction, the second height different from the first height.Type: GrantFiled: January 17, 2020Date of Patent: September 5, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Sheng-Hsiung Chen, Chun-Chen Chen, Shao-huan Wang, Kuo-Nan Yang, Chung-Hsing Wang, Ren-Zheng Liao, Meng-Xiang Lee
-
Patent number: 11727185Abstract: A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.Type: GrantFiled: July 26, 2022Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou
-
Patent number: 11704472Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.Type: GrantFiled: November 10, 2021Date of Patent: July 18, 2023Assignee: Taiwan Semiconductor Manufacutring Co., Ltd.Inventors: Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen
-
Patent number: 11681853Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.Type: GrantFiled: March 11, 2022Date of Patent: June 20, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Hsiung Chen, Wen-Hao Chen, Hung-Chih Ou, Chun-Yao Ku, Shao-Huan Wang
-
Patent number: 11669669Abstract: A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.Type: GrantFiled: July 30, 2020Date of Patent: June 6, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chin-Shen Lin, Wan-Yu Lo, Shao-Huan Wang, Kuo-Nan Yang, Chung-Hsing Wang, Sheng-Hsiung Chen, Huang-Yu Chen
-
Publication number: 20220367358Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Inventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
-
Publication number: 20220358277Abstract: A system includes a non-transitory computer readable medium configured to store instructions thereon. The system further includes a processor connected to the non-transitory computer readable medium. The processor is configured to execute the instruction for comparing a size of a via pillar structure of a first layout pattern of a plurality of layout patterns with a size of a via pillar structure of a second layout pattern of the plurality of layout patterns, wherein each of the plurality of layout patterns meets an electromigration (EM) rule. The processor is further configured to execute the instructions for replacing, in a layout design, the first layout pattern with the second layout pattern in response to the size of the via pillar structure of the second layout pattern being less than the size of the via pillar structure of the first layout pattern.Type: ApplicationFiled: July 26, 2022Publication date: November 10, 2022Inventors: Shao-Huan WANG, Sheng-Hsiung CHEN, Wen-Hao CHEN, Chun-Chen CHEN, Hung-Chih OU
-
Patent number: 11449656Abstract: A method including selecting a plurality of layout patterns, wherein each of the layout patterns comprises a corresponding via pillar structure that satisfies an electromigration (EM) rule, wherein each of the via pillar structures comprises metal layers and at least one via coupled to the metal layers. The method further includes selecting a layout pattern from the plurality of layout patterns having a smallest physical size. The method further includes performing a placement and routing process by using the selected layout pattern.Type: GrantFiled: September 23, 2020Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Chen Chen, Hung-Chih Ou
-
Patent number: 11437319Abstract: An integrated circuit includes a cell that is between a substrate and a supply conductive line and that includes a source region, a contact conductive line, a power conductive line, and a power via. The contact conductive line extends from the source region. The power conductive line is coupled to the contact conductive line. The power via interconnects the supply conductive line and the power conductive line.Type: GrantFiled: October 8, 2020Date of Patent: September 6, 2022Assignee: Taiwan Semiconductor Manufacturing Company LimitedInventors: Sheng-Hsiung Chen, Chung-Hsing Wang, Fong-yuan Chang, Lee-Chung Lu, Li-Chun Tien, Po-Hsiang Huang, Shao-huan Wang, Ting Yu Chen, Yen-Pin Chen, Chun-Chen Chen, Tzu-Hen Lin, Tai-Yu Cheng
-
Publication number: 20220198122Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop and a first inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.Type: ApplicationFiled: March 11, 2022Publication date: June 23, 2022Inventors: Sheng-Hsiung CHEN, Wen-Hao CHEN, Hung-Chih OU, Chun-Yao KU, Shao-Huan WANG
-
Patent number: 11275886Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop, a first inverter, and a second inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The second inverter is coupled to the first inverter, is configured to receive the second clock signal, and is configured to generate a third clock signal inverted from the second clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.Type: GrantFiled: April 20, 2021Date of Patent: March 15, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sheng-Hsiung Chen, Wen-Hao Chen, Chun-Yao Ku, Shao-Huan Wang, Hung-Chih Ou
-
Publication number: 20220067266Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.Type: ApplicationFiled: November 10, 2021Publication date: March 3, 2022Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Sheng-Hsiung CHEN, Jerry Chang-Jui KAO, Fong-Yuan CHANG, Po-Hsiang HUANG, Shao-Huan WANG, XinYong WANG, Yi-Kan CHENG, Chun-Chen CHEN
-
Publication number: 20220035982Abstract: A method for manufacturing a semiconductor device is provided. The method comprises determining a dimensional quantity of a layout pattern having an angle relative to grid lines of a minimum grid. The minimum grid may be defined by a first quantity associated with a first direction and a second quantity associated with a second direction perpendicular to the first direction. The determination of the dimensional quantity of the layout pattern is based on the first quantity, the second quantity and the angle of the layout pattern relative to the grid lines of the minimum grid.Type: ApplicationFiled: July 30, 2020Publication date: February 3, 2022Inventors: CHIN-SHEN LIN, WAN-YU LO, SHAO-HUAN WANG, KUO-NAN YANG, CHUNG-HSING WANG, SHENG-HSIUNG CHEN, HUANG-YU CHEN
-
Patent number: 11182533Abstract: Standard cell libraries include one or more standard cells and one or more corresponding standard cell variations. The one or more standard cell variations are different from their one or more standard cells in terms of geometric shapes, locations of the geometric shapes, and/or interconnections between the geometric shapes. The exemplary systems and methods described herein selectively choose from among the one or more standard cells and/or the one or more standard cell variations to form an electronic architectural design for an electronic device. In some situations, some of the one or more standard cells are unable to satisfy one or more electronic design constraints imposed by a semiconductor foundry and/or semiconductor technology node when placed onto the electronic device design real estate. In these situations, the one or more standard cell variations corresponding to these standard cells are placed onto the electronic device design real estate.Type: GrantFiled: June 25, 2020Date of Patent: November 23, 2021Inventors: Sheng-Hsiung Chen, Jerry Chang-Jui Kao, Fong-Yuan Chang, Po-Hsiang Huang, Shao-Huan Wang, XinYong Wang, Yi-Kan Cheng, Chun-Chen Chen
-
Patent number: 11170149Abstract: A method for outputting a first number of subsets of a layer pattern comprising a plurality of cells arranged in a row includes selecting subsets of cells from the plurality of cells, constructing a graph representation for each subset of cells, identifying graph representations that are not colorable with a first number of labels, identifying subsets of cells that correspond to the identified graph representations, changing a distance between cells in each of the identified subset of cells, wherein the changed distances are greater than the first spacing, labeling the graph representations with the first number of labels, and outputting subsets of the layer pattern to a machine readable storage medium for manufacturing a set of masks that is used to form a single, patterned layer. Each subset of the layer pattern represents a separate mask pattern and includes features of the layer pattern corresponding to a label in the labeled graph representations.Type: GrantFiled: November 21, 2019Date of Patent: November 9, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Shao-Huan Wang, Sheng-Hsiung Chen, Fong-Yuan Chang, Po-Hsiang Huang
-
Publication number: 20210256193Abstract: A multi-bit flip-flop includes a first flip-flop, a second flip-flop, a first inverter, and a second inverter. The first flip-flop has a first driving capability. The second flip-flop has a second driving capability different from the first driving capability. The first inverter is configured to receive a first clock signal on a first clock pin, and is configured to generate a second clock signal inverted from the first clock signal. The second inverter is coupled to the first inverter, is configured to receive the second clock signal, and is configured to generate a third clock signal inverted from the second clock signal. The first flip-flop and the second flip-flop are configured to share at least the first clock pin.Type: ApplicationFiled: April 20, 2021Publication date: August 19, 2021Inventors: Sheng-Hsiung CHEN, Wen-Hao CHEN, Chun-Yao KU, Shao-Huan WANG, Hung-Chih OU