Patents by Inventor Shao-Jung Wang

Shao-Jung Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240171074
    Abstract: A switching regulator includes: a power stage circuit, a control circuit and an operation clock signal generator circuit. The operation clock signal generator circuit includes: a time point option unit generating a time point option signal according to a phase node voltage during a ringing period subsequent to a blanking period, to indicate at least one available turn-on time point, or generating a lowest voltage time point signal according to the phase node voltage during a tolerance period, to indicate a lowest voltage time point; and a time point deciding unit deciding the tolerance period according to a base clock signal and a tolerable frequency range and select the available turn-on time point or the lowest voltage time point within the tolerance period as a decided time point, to generate the operation clock signal.
    Type: Application
    Filed: October 25, 2023
    Publication date: May 23, 2024
    Inventors: Jiing-Horng Wang, Yu-Pin Tseng, Chia-Jung Chang, Tsan-He Wang, Shao-Ming Chang
  • Publication number: 20240128868
    Abstract: A switching regulator includes: a power stage circuit; a control circuit; and an operation clock signal generator circuit configured to generate plural test clock signals during a clock determination period and generate an operation clock signal during a normal operation period. When the switching regulator operates during the clock determination period in a discontinuous conduction mode, the control circuit alternatingly generates plural PWM signals corresponding to the test clock signals generated by the operation clock signal generator circuit and an output voltage, wherein each PWM signal corresponds to one test clock signal, so that the power stage circuit generates corresponding phase node voltages at a phase node, wherein among the plural test clock signals, the operation clock signal generator circuit selects one test clock signal corresponding to a minimum phase node voltage as the operation clock signal during the normal operation period.
    Type: Application
    Filed: September 21, 2023
    Publication date: April 18, 2024
    Inventors: Chia-Jung Chang, Shao-Ming Chang, Tsan-He Wang, Jiing-Horng Wang, Yu-Pin Tseng
  • Publication number: 20100287317
    Abstract: A source driver system includes a scan driver and a data driver. The data driver has a signal controller, a data bus, a connector and a plurality of data driver units. The signal controller is connected with the connector with via the data bus to form a first connection relationship such that the data bus is capable of transmitting control signals from the signal controller to the connector. The connector connects with the data driver units via the data bus to form a second connection relationship such that the data bus is capable of transmitting the control signals from the connector to the corresponding data driver units. In a preferred embodiment, the data bus is further arranged to form a third connection relationship among the data driver units such that the data bus is capable of communicating a serial connection signal among the data driver units.
    Type: Application
    Filed: August 17, 2009
    Publication date: November 11, 2010
    Inventors: Wan-Hsiang Shen, Jyh-Ting Lai, Wei-Kang Hsu, Wei-Bo Su, Shao-Jung Wang, Jen-Hung Tung