Abstract: A modular computational structure includes a pipeline having first and second adder stages. Each adder stage includes a pair of adders which operate in parallel, and outputs ports of the first adder stage are coupled to input ports of the second adder stage. Rounding logic and an accumulator are included in the second stage. By varying the inputs to the first and second stages a variety of complex arithmetic functions suitable for video encoding can be implemented. Examples of the operations include completion of multiply and multiply-and-accumulate operations, averages of two values, averages of four values, and merged difference and absolute value calculation.

Abstract: A floating point unit (FPU) is described which processes normalized binary numbers. All multiply, add, and subtract calculations are performed using the format (A*B)+C or (A*B)-C. The operation A*B is performed in parallel with the alignment of C to the product of A*B. An output of the multiplier and the aligned operand C are applied to a carry save adder, whose output is then applied to a carry propagate adder to generate the result A*B.+-.C. The output of the carry save adder is also applied to a combined leading one anticipator (LOA) and leading zero anticipator (LZA). The output of the carry propogate adder is provided to a post normalizer. The output of the combined LOA/LZA is applied to the input of a multiplexer, with the control input of the multiplexer being connected to the most significant bit of the adder output, where this most significant bit indicates whether the result is positive or negative.

Abstract: A two-bit Booth multiplier circuit performs two-bit multiplication iterations using a single adder while retaining the same data path width and the multiplicand multiples of a single-bit Booth multiplier circuit. The two-bit Booth multiplier circuit halves the number of multiplier iterations of a single-bit multiplier. A multiplier circuit includes an adder having a first input terminal, a second input terminal, and an output terminal and a plurality of shift registers. The registers include a multiplicand register having an output terminal connected to the first input terminal of the adder, a temporary shift register having an output terminal connected to the second input terminal of the adder and having an input terminal connected to the output terminal of the adder, and a multiplier shift register having an input terminal connected to the output terminal of the adder and the multiplier shift register and having an output terminal.

Abstract: An adder circuit includes various methods to control the carry bit at data boundaries when attempting to process multiple data of multiple types. One method is to generate both propagate and generate signals from the input data and modified propagate and generate signals from the data boundaries, which can then be used in a conventional carry-lookahead adder to produce a resulting sum that is correct regardless of the data type being processed. Another method is to insert special carry blocking, propagating or generating cells at the data boundaries of the input data. These cells are then filled with the appropriate blocking, propagating or generating signals, either by table look-up or circuit implementation using data type and processing type inputs. This data stream can then be added with a conventional adder. However, if the special cell replaces data at the boundaries, another adder can be used to process this boundary data separately prior to inserting the special cell.

Abstract: A fused floating point multiply-and-accumulate unit includes a multiplier which uses a modified Booth's algorithm to generate a sum and a carry representing a product of mantissas. An artifact of this algorithm is that the sum or carry may represent a negative value even though both mantissas are positive. The negative value may have a sign bit from sign extension or sign encoding of partial products in the multiplier. An artifact of the signed bit is a false carry out that results from canceling the sign bit. A 3-input adder simultaneously combines the sum and carry from the multiplier and performs the accumulation. The adder includes carry correction logic to suppress false carries and prevents a false carry from affecting more significant bits of the value being accumulated.

Abstract: A floating point multiply-and-accumulate unit that performs an operation A*B.+-.C also determines an exponent difference (Ea+Eb)-Ec where Ea, Eb, and Ec are the exponents of values A, B, and C. The exponent difference indicates a class for the operation. In a first class, C is much greater than A*B and accumulation of a mantissa Mc of C with a mantissa Ma*Mb of A*B leaves mantissa Mc. In second and third classes, C and A*B are comparable and mantissas Mc and Ma*Mb overlap during accumulation. In a fourth class, A*B is much greater than C so that accumulation of mantissas Mc and Ma*Mb leaves Ma*Mb. The classes controls shift logic for alignment before accumulation or postnormalization after accumulation. For the first class, alignment or normalization are fixed according to Mc. For the second and third class, a fixed shift for alignment or normalization according to Ma*Mb is performed followed by a variable shift as indicated either by the exponent difference or cancellation detected during accumulation.