Patents by Inventor Shao Ming Koh

Shao Ming Koh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230123827
    Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.
    Type: Application
    Filed: December 19, 2022
    Publication date: April 20, 2023
    Inventors: Shao-Ming Koh, Chen-Ming Lee, Fu-Kai Yang
  • Patent number: 11532504
    Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.
    Type: Grant
    Filed: August 5, 2020
    Date of Patent: December 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, Fu-Kai Yang
  • Patent number: 11217492
    Abstract: A method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, and a first source/drain (S/D) feature and a second S/D feature over the substrate. The first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, the first S/D feature is configured for an n-type transistor, and the second S/D feature is configured for a p-type transistor. The method further includes introducing a p-type dopant into both the first and the second S/D features. After the introducing of the p-type dopant, the method further includes performing an etching process to the first and the second S/D features, wherein the etching process etches the first S/D feature faster than it etches the second S/D feature.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: January 4, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Jia-Heng Wang, Mei-Yun Wang
  • Patent number: 11145554
    Abstract: A semiconductor device includes an n-type FET device and a p-type FET device. The n-type FET device includes a first substrate region, a first gate stack, a first gate spacer over sidewalls of the first gate stack, and an n-type epitaxial feature in a source/drain (S/D) region of the n-type FET device. The p-type FET device includes a second substrate region, a second gate stack, a second gate spacer over sidewalls of the second gate stack, and a p-type epitaxial feature in an S/D region of the p-type FET device. A vertical distance between a bottom surface of the first gate spacer and a lowest point of an upper surface of the n-type epitaxial feature is greater than a vertical distance between a bottom surface of the second gate spacer and a lowest point of an upper surface of the p-type epitaxial feature.
    Type: Grant
    Filed: November 19, 2019
    Date of Patent: October 12, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Jia-Heng Wang, Mei-Yun Wang
  • Publication number: 20210313324
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiments, a semiconductor device includes an n-type transistor region and a p-type transistor region. The n-type transistor region includes a first gate stack, a first gate spacer over sidewalls of the first gate stack, an n-type epitaxial feature in a source/drain (S/D) region of the n-type transistor region, and a first metal silicide layer over the n-type epitaxial feature. The p-type transistor region includes a second gate stack, a second gate spacer over sidewalls of the second gate stack, a p-type epitaxial feature in an S/D region of the p-type transistor region, a dopant-containing implant layer over the p-type epitaxial feature, and a second metal silicide layer over the dopant-containing implant layer. The dopant-containing implant layer includes a metallic dopant.
    Type: Application
    Filed: June 14, 2021
    Publication date: October 7, 2021
    Inventors: Shao-Ming Koh, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Patent number: 11037924
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiments, the method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, a first source/drain (S/D) feature comprising silicon adjacent to the first gate structure, a second S/D feature comprising silicon germanium (SiGe) adjacent to the second gate structure; and one or more dielectric layers over sidewalls of the first and second gate structures and over the first and second S/D features. The method further includes etching the one or more dielectric layers to form openings exposing the first and second S/D features, forming a masking layer over the first S/D feature, implanting gallium (Ga) into the second S/D feature while the masking layer is over the first S/D feature, removing the masking layer; and etching the first and second S/D features with an oxygen-atom-containing etchant.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: June 15, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20200365450
    Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.
    Type: Application
    Filed: August 5, 2020
    Publication date: November 19, 2020
    Inventors: Shao-Ming Koh, Chen-Ming Lee, Fu-Kai Yang
  • Patent number: 10741438
    Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: August 11, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, Fu-Kai Yang
  • Publication number: 20200083118
    Abstract: A semiconductor device includes an n-type FET device and a p-type FET device. The n-type FET device includes a first substrate region, a first gate stack, a first gate spacer over sidewalls of the first gate stack, and an n-type epitaxial feature in a source/drain (S/D) region of the n-type FET device. The p-type FET device includes a second substrate region, a second gate stack, a second gate spacer over sidewalls of the second gate stack, and a p-type epitaxial feature in an S/D region of the p-type FET device. A vertical distance between a bottom surface of the first gate spacer and a lowest point of an upper surface of the n-type epitaxial feature is greater than a vertical distance between a bottom surface of the second gate spacer and a lowest point of an upper surface of the p-type epitaxial feature.
    Type: Application
    Filed: November 19, 2019
    Publication date: March 12, 2020
    Inventors: Shao-Ming Koh, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Jia-Heng Wang, Mei-Yun Wang
  • Publication number: 20200083119
    Abstract: A method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, and a first source/drain (S/D) feature and a second S/D feature over the substrate. The first S/D feature is adjacent to the first gate structure, the second S/D feature is adjacent to the second gate structure, the first S/D feature is configured for an n-type transistor, and the second S/D feature is configured for a p-type transistor. The method further includes introducing a p-type dopant into both the first and the second S/D features. After the introducing of the p-type dopant, the method further includes performing an etching process to the first and the second S/D features, wherein the etching process etches the first S/D feature faster than it etches the second S/D feature.
    Type: Application
    Filed: November 19, 2019
    Publication date: March 12, 2020
    Inventors: Shao-Ming Koh, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Jia-Heng Wang, Mei-Yun Wang
  • Patent number: 10490459
    Abstract: A method includes providing a structure that includes a substrate; first and second gate structures over the substrate; first and second source/drain (S/D) features over the substrate; a first dielectric layer over sidewalls of the first and second gate structures and the first and second S/D features; and a second dielectric layer over the first dielectric layer. The first and second S/D features are adjacent to the first and second gate structures respectively. The first and second S/D features comprise different materials. The method further includes etching the first and second dielectric layers to expose the first and second S/D features; doping a p-type dopant to the first and second S/D features; and performing a selective etching process to the first and second S/D features after the doping of the p-type dopant. The selective etching process recesses the first S/D feature faster than it recesses the second S/D feature.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: November 26, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Jia-Heng Wang, Mei-Yun Wang
  • Publication number: 20190157269
    Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiments, the method includes providing a structure that includes a substrate, a first gate structure and a second gate structure over the substrate, a first source/drain (S/D) feature comprising silicon adjacent to the first gate structure, a second S/D feature comprising silicon germanium (SiGe) adjacent to the second gate structure; and one or more dielectric layers over sidewalls of the first and second gate structures and over the first and second S/D features. The method further includes etching the one or more dielectric layers to form openings exposing the first and second S/D features, forming a masking layer over the first S/D feature, implanting gallium (Ga) into the second S/D feature while the masking layer is over the first S/D feature, removing the masking layer; and etching the first and second S/D features with an oxygen-atom-containing etchant.
    Type: Application
    Filed: January 10, 2018
    Publication date: May 23, 2019
    Inventors: Shao-Ming Koh, Chen-Ming Lee, Fu-Kai Yang, Mei-Yun Wang
  • Publication number: 20190115249
    Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.
    Type: Application
    Filed: December 10, 2018
    Publication date: April 18, 2019
    Inventors: Shao-Ming Koh, Chen-Ming Lee, Fu-Kai Yang
  • Publication number: 20190067130
    Abstract: A method includes providing a structure that includes a substrate; first and second gate structures over the substrate; first and second source/drain (S/D) features over the substrate; a first dielectric layer over sidewalls of the first and second gate structures and the first and second S/D features; and a second dielectric layer over the first dielectric layer. The first and second S/D features are adjacent to the first and second gate structures respectively. The first and second S/D features comprise different materials. The method further includes etching the first and second dielectric layers to expose the first and second S/D features; doping a p-type dopant to the first and second S/D features; and performing a selective etching process to the first and second S/D features after the doping of the p-type dopant. The selective etching process recesses the first S/D feature faster than it recesses the second S/D feature.
    Type: Application
    Filed: August 25, 2017
    Publication date: February 28, 2019
    Inventors: Shao-Ming Koh, Chen-Ming Lee, I-Wen Wu, Fu-Kai Yang, Jia-Heng Wang, Mei-Yun Wang
  • Patent number: 10153198
    Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.
    Type: Grant
    Filed: April 7, 2017
    Date of Patent: December 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ming Koh, Chen-Ming Lee, Fu-Kai Yang
  • Publication number: 20180294184
    Abstract: A method includes forming a first and a second contact opening to reveal a first and a second source/drain region, respectively, forming a mask layer having a first and a second portion in the first and the second contact openings, respectively, forming a first and a second sacrificial ILD in the first and the second contact openings, respectively, removing the first sacrificial ILD from the first contact opening, filling a filler in the first contact opening, and etching the second sacrificial ILD. The filler protects the first portion of the mask layer from being etched. An ILD is formed in the second contact opening and on the second portion of the mask layer. The filler and the first portion of the mask layer are removed using a wet etch to reveal the first contact opening. A contact plug is formed in the first contact opening.
    Type: Application
    Filed: April 7, 2017
    Publication date: October 11, 2018
    Inventors: Shao-Ming Koh, Chen-Ming Lee, Fu-Kai Yang
  • Patent number: 9660075
    Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: May 23, 2017
    Assignee: GLOBALFOUNDRIES, INC.
    Inventors: Shao Ming Koh, Guillaume Bouche, Jeremy A. Wahl, Andy C. Wei
  • Patent number: 9490340
    Abstract: A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: November 8, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shao-Ming Koh, Guillaume Bouche, Jing Wan, Andy C. Wei
  • Patent number: 9431512
    Abstract: A method of forming a nanowire device includes forming semiconductor material layers above a semiconductor substrate, forming a gate structure above the semiconductor material layers, forming a first sidewall spacer adjacent to the gate structure and forming a second sidewall spacer adjacent to the first sidewall spacer. The method further includes patterning the semiconductor material layers such that each layer has first and second exposed end surfaces. The gate structure, the first sidewall spacer, and the second sidewall spacer are used in combination as an etch mask during the patterning process. The method further includes removing the first and second sidewall spacers, thereby exposing at least a portion of the patterned semiconductor material layers. The method further includes forming doped extension regions in at least the exposed portions of the patterned semiconductor material layers after removing the first and second sidewall spacers.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: August 30, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shao-Ming Koh, Guillaume Bouche, Jing Wan, Andy C. Wei
  • Publication number: 20160172493
    Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with fin structures having source/drain regions in PFET areas and in NFET areas. The method includes selectively forming a contact resistance modulation material on the source/drain regions in the PFET areas. Further, the method includes depositing a band-edge workfunction metal overlying the source/drain regions in the PFET areas and in the NFET areas.
    Type: Application
    Filed: February 24, 2016
    Publication date: June 16, 2016
    Inventors: Shao Ming Koh, Guillaume Bouche, Jeremy A. Wahl, Andy C. Wei