Abstract: A signal processing system is provided. The system includes a calculating apparatus, for calculating a phase error of a received signal and generating a weight according to the phase error; a signal adjusting apparatus, coupled to the calculating apparatus, for generating a plurality of soft values according to the weight and the received signal; and a decoder, coupled to the signal adjusting apparatus, for decoding the soft values to generate data.

Abstract: A phase digitizing apparatus for generating a corresponding digital value in response to a phase of an input signal is provided. The phase digitizing apparatus includes a coarse phase generator, for generating a coarse phase code according to the phase of the input signal and a first time unit; a fine phase code generator, for generating a fine phase code according to the phase of the input signal and a second time unit; and a calculating unit, for generating the digital value according to the coarse phase code and the fine phase code; wherein the first time unit is greater than the second time unit.

Abstract: A spread spectrum clock signal generator for spreading an input clock signal into an output clock signal includes a clock signal delay chain for delaying the input clock signal into a delay clock signal group having a plurality of delay clock signals, a modulation controller for outputting a counter clock signal control signal, a clock signal selection circuit for selecting, from the delay clock signal group, a modulation clock signal group having a plurality of modulation clock signals, a programmable counter for generating a counting value according to a counter clock signal, and a clock signal output unit for combining the modulation clock signals into the output clock signal according to the counting value, and further generating the counter clock signal, outputted to the programmable counter, according to the counter clock signal control signal.

Abstract: A source driving apparatus and a driving method thereof are provided. The source driving apparatus comprises an encoder and a source driver. The encoder encodes a video data with n bits to the encoded data according to encoding rules, such that the bit change in two adjacent grays is less than n. The source driver outputs a pixel voltage corresponding to the video data according to the encoded data.

Abstract: A communication device including a receiving unit and a signal processing module having a simulation unit and a decision unit is provided. The receiving unit receives a first burst of a paging message provided from a base station. Base on a reference burst code and an estimated channel impulse response of the communication channel, the simulation unit generates a simulation burst. The decision unit then determines if the paging message is a dummy message in accordance with the first burst and the simulation burst. The decision unit requests the receiving unit to stop receiving the paging message once the paging message is determined to be a dummy message.

Abstract: A phase digitizing apparatus for generating a corresponding digital value in response to a phase of an input signal is provided. The phase digitizing apparatus includes a coarse phase generator, for generating a coarse phase code according to the phase of the input signal and a first time unit; a fine phase code generator, for generating a fine phase code according to the phase of the input signal and a second time unit; and a calculating unit, for generating the digital value according to the coarse phase code and the fine phase code; wherein the first time unit is greater than the second time unit.

Abstract: A signal processing circuit is provided. The signal processing circuit, adjusting a received radio frequency (RF) signal according to a gain, and generating a digital signal accordingly, the signal processing circuit including a signal analysis circuit, for analyzing the digital signal to generate the gain, determining whether the received RF signal is a target signal, and generating a reference value according to the digital signal, and a baseband circuit, for performing a carrier frequency offset (CFO) compensation to the digital signal according to the reference value, wherein, the reference value is generated while the signal analysis circuit is determining whether the received RF signal is the target signal.

Abstract: A determining method and apparatus thereof for a transition point of a sequence which can be applied to a decoder. The determining method determines the transition point of the sequence having N numbers, wherein the sequence is composed of a first value and a second value and N is a positive integer. The determining method includes determining the position the first value appearing consecutively in the sequence to determine a first interval; determining the position the second value appearing consecutively in the sequence to determine a second interval; and determining the longer interval between the first interval and the second interval, when the first interval is longer, determining an adjacency of the first interval and the second value as the transition point according to the first interval, and when the second interval is longer, determining an adjacency of the second interval and the first value as the transition point.

Abstract: A signal processing apparatus for determining whether a receiving signal is a target signal is provided. The apparatus includes: a sampling device for sampling the receiving signal to generate a plurality of sampled values; a first calculation device, coupled to the sampling device, for generating a plurality of first values according to the sampled values and a plurality of reference values; a second calculation device, coupled to the first calculation device, for grouping the first values into a plurality of value groups, respectively calculating the value groups to generate a plurality of second values and generating a determination value by calculating the second values; and a determination device, coupled to the second calculation device, for determining whether the receiving signal is the target signal by comparing the determination value with a threshold value.

Abstract: A signal processing system is provided. The system includes a calculating apparatus, for calculating a phase error of a received signal and generating a weight according to the phase error; a signal adjusting apparatus, coupled to the calculating apparatus, for generating a plurality of soft values according to the weight and the received signal; and a decoder, coupled to the signal adjusting apparatus, for decoding the soft values to generate data.

Abstract: A method and associated apparatus using delay correlation for determining whether an input signal is a target signal is provided. The method includes sampling the input signal to generate 2N sample values, the sample values having a period N, where N is a positive integer; calculating the 2N sample values to obtain a first value according to a first operation method; calculating the 2N sample values to obtain a second value according to a second operation method; obtaining a determination value according to the first value and the second value; and determining whether the input signal is the target signal according to the determination value and a threshold.

Abstract: A soft decision method for determining a soft decision coordinate associated with a constellation is provided. The soft decision coordinate includes a first soft decision sub-coordinate and a second soft decision sub-coordinate. The method includes receiving an input signal including a coordinate value; defining a first coordinate range on a coordinate axis in the constellation, the first coordinate range having a first limit and a second limit; obtaining the first soft decision sub-coordinate according to the first coordinate range; defining a second coordinate range on the coordinate axis in the constellation, the second coordinate range having a third limit and a fourth limit; and obtaining the second soft decision sub-coordinate according to the second coordinate range; wherein the first and the third limit do not simultaneously equal to the second and the fourth limit.

Abstract: A decoding method for determining a preferred survivor path in a decoding process is provided. The method includes calculating a first determination value of a first survivor path at a first time point, the first determination value being determined by a first sub determination value and a second determination value at a second time point, and the second time point being prior to the first time point; calculating a third determination value of a second survivor path at the first time point, the third determination value being determined by a second sub determination value and a fourth determination value at the second time point; and when a difference between the first determination value and the third determination value is equal to or less than a predetermined value, determining the preferred survivor path at the first time point according to the second and the fourth determination values, or the first and the second sub determination values.

Abstract: A source driving apparatus and a driving method thereof are provided. The source driving apparatus comprises an encoder and a source driver. The encoder encodes a video data with n bits to the encoded data according to encoding rules, such that the bit change in two adjacent grays is less than n. The source driver outputs a pixel voltage corresponding to the video data according to the encoded data.

Abstract: A spread spectrum clock signal generator for spreading an input clock signal into an output clock signal includes a clock signal delay chain for delaying the input clock signal into a delay clock signal group having a plurality of delay clock signals, a modulation controller for outputting a counter clock signal control signal, a clock signal selection circuit for selecting, from the delay clock signal group, a modulation clock signal group having a plurality of modulation clock signals, a programmable counter for generating a counting value according to a counter clock signal, and a clock signal output unit for combining the modulation clock signals into the output clock signal according to the counting value, and further generating the counter clock signal, outputted to the programmable counter, according to the counter clock signal control signal.

Abstract: A level shifter consisting of first to fifth transistors is provided. First ends of the first and second transistors are coupled to a first supply voltage. Control ends of third and fourth transistors respectively receive first and second input signals. First ends of the third and fourth transistors are respectively coupled to control ends of the second and first transistors, and are respectively coupled to second ends of the first and second transistors. Second ends of the third and fourth transistors are coupled to a second supply voltage. The first ends of the third and fourth transistors respectively output first and second output signals. A first end and a control end of the fifth transistor are coupled to the control ends of one and the other of the first and second transistors. A second end of the fifth transistor is coupled to the second supply voltage.

Abstract: The present invention discloses a method and apparatus of IQ imbalance compensation for a receiver. The repetitive attribute of the preamble in a signal received by the receiver is used to estimate the IQ imbalance parameters. The data carried by the preamble repeats itself every N sampling intervals. A MSE equation is derived based on assuming the ratios between any two sampling points separated by N samples are identical, and the IQ imbalance parameters can be estimated by solving the MSE equation using the LS algorithm. Consequently, the IQ mismatch offset of the signal is compensated according to the estimated parameters.

Abstract: A scan driver for a liquid crystal display (LCD) includes first and second address logic units, first and second level shifters and a decoder. The first address logic unit enables an ith first address signal among N first address signals during a Kth clock period according to a control signal, wherein the number i is equal to a remainder of K/N. The second address logic unit enables a jth second address signal among M second address signals during the Kth clock period according to the control signal, wherein the number j is equal to a quotient of K/N plus 1. The first and second level shifters respectively increase swings of the first and second address signals. When the ith first address signal and the jth second address signal are enabled, the decoder enables a (j?1)×N+i)th scan signal among M×N scan signals.

Abstract: The present invention discloses a method for prevention of distorted sub-picture display on a flat panel display. The display image of the flat panel display comprises a main picture and a sub-picture. While a drop line is performed on the main picture, image data output of the sub-picture is stopped. As the drop line is finished, image data output of the sub-picture is resumed. The method of stopping the output of image data of the sub-picture is adopted as a way to stop outputting a timing control signal used for controlling the image data output of the sub-picture, wherein the timing control signal is a horizontal synchronization signal or a clock signal. The timing control signal does not change logic state level while the drop line occurs. The image data of the sub-picture will not be discarded or masked while the drop line occurs. This prevents a distorted sub-picture on the flat panel display.

Abstract: The present invention discloses a method and apparatus of IQ imbalance compensation for a receiver. The repetitive attribute of the preamble in a signal received by the receiver is used to estimate the IQ imbalance parameters. The data carried by the preamble repeats itself every N sampling intervals. A MSE equation is derived based on assuming the ratios between any two sampling points separated by N samples are identical, and the IQ imbalance parameters can be estimated by solving the MSE equation using the LS algorithm. Consequently, the IQ mismatch offset of the signal is compensated according to the estimated parameters.