Patents by Inventor Shao-Ta Hsu
Shao-Ta Hsu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8921977Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.Type: GrantFiled: December 21, 2011Date of Patent: December 30, 2014Assignee: Nan Ya Technology CorporationInventors: Jen Jui Huang, Che Chi Lee, Shih Shu Tsai, Cheng Shun Chen, Shao Ta Hsu, Chao Wen Lay, Chun I Hsieh, Ching Kai Lin
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Publication number: 20130161786Abstract: A capacitor array includes a plurality of capacitors and a support frame. Each capacitor includes an electrode. The support frame supports the plurality of electrodes and includes a plurality of support structures corresponding to the plurality of electrodes. Each support structure may surround the respective electrode. The support frame may include oxide of a doped oxidizable material.Type: ApplicationFiled: December 21, 2011Publication date: June 27, 2013Applicant: Nan Ya Technology CorporationInventors: Jen Jui Huang, Che Chi Lee, Shih Shu Tsai, Cheng Shun Chen, Shao Ta Hsu, Chao Wen Lay, Chun I. Hsieh, Ching Kai Lin
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Patent number: 7642166Abstract: A method of manufacturing a MOS transistor device is provided. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.Type: GrantFiled: November 6, 2008Date of Patent: January 5, 2010Assignee: United Microelectronics Corp.Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Neng-Kuo Chen, Shao-Ta Hsu, Teng-Chun Tsai, Chien-Chung Huang
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Patent number: 7541298Abstract: A method for filling silicon oxide materials into a trench includes providing a substrate having a plurality of trenches, performing a first deposition process to form a first silicon oxide layer in the trenches, and performing a second deposition process to form a second silicon oxide layer in the trenches. The reactant gas of the first deposition process has a first O3/TEOS flow ratio larger than a second O3/TEOS flow ratio of the reactant gas of the second deposition process.Type: GrantFiled: January 10, 2007Date of Patent: June 2, 2009Assignee: United Microelectronics Corp.Inventors: Shao-Ta Hsu, Neng-Kuo Chen, Teng-Chun Tsai
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Publication number: 20090068805Abstract: A method of manufacturing a MOS transistor device is provided. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.Type: ApplicationFiled: November 6, 2008Publication date: March 12, 2009Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Neng-Kuo Chen, Shao-Ta Hsu, Teng-Chun Tsai, Chien-Chung Huang
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Patent number: 7494878Abstract: A method of manufacturing a MOS transistor device. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.Type: GrantFiled: October 25, 2006Date of Patent: February 24, 2009Assignee: United Microelectronics Corp.Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Neng-Kuo Chen, Shao-Ta Hsu, Teng-Chun Tsai, Chien-Chung Huang
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Publication number: 20080185655Abstract: A method for forming a semiconductor device is provided. The method comprises steps of providing a substrate having a first-conductive-type transistor and a second-conductive-type transistor formed thereon and then forming a stress layer over the substrate to conformally cover the first-conductive-type transistor and the second-conductive-type transistor. A cap layer is formed on the stress layer over the first-conductive-type transistor. A modification process is performed. The cap layer is removed.Type: ApplicationFiled: February 2, 2007Publication date: August 7, 2008Applicant: UNITED MICROELECTRONICS CORP.Inventors: Shao-Ta Hsu, Teng-Chun Tsai, Neng-Kuo Chen, Hsiu-Lien Liao, Cheng-Han Wu, Wen-Han Hung
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Publication number: 20080188091Abstract: A method for forming a semiconductor device is provided. The method comprises steps of providing a substrate having a first-conductive-type transistor and a second-conductive-type transistor formed thereon and then forming a stress layer over the substrate to conformally cover the first-conductive-type transistor and the second-conductive-type transistor. A cap layer is formed on the stress layer over the first-conductive-type transistor. A modification process is performed. The cap layer is removed.Type: ApplicationFiled: March 6, 2008Publication date: August 7, 2008Inventors: SHAO-TA HSU, Teng-Chun Tsai, Neng-Kuo Chen, Hsiu-Lien Liao, Cheng-Han Wu, Wen-Han Hung
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Publication number: 20080166888Abstract: A method for filling silicon nitride materials into a trench includes providing a substrate having a plurality of trenches, performing a first deposition process to form a first silicon nitride layer in the trenches, and performing a second deposition process to form a second silicon nitride layer in the trenches. The reactant gas of the first deposition process has a first O3/TEOS flow ratio larger than a second O3/TEOS flow ratio of the reactant gas of the second deposition process.Type: ApplicationFiled: January 10, 2007Publication date: July 10, 2008Inventors: Shao-Ta Hsu, Neng-Kuo Chen, Teng-Chun Tsai
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Publication number: 20080099801Abstract: A method of manufacturing a MOS transistor device. First, a semiconductor substrate having a gate structure is prepared. The gate structure has two sidewalls and a liner on the sidewalls. Subsequently, a stressed cap layer is formed on the semiconductor substrate, and covers the gate structure and the liner. Next, an activating process is performed. Furthermore, the stressed cap layer is etched to be a salicide block. Afterward, a salicide process is performed to form a silicide layer on the regions that are not covered by the stressed cap layer.Type: ApplicationFiled: October 25, 2006Publication date: May 1, 2008Inventors: Kun-Hsien Lee, Cheng-Tung Huang, Wen-Han Hung, Shyh-Fann Ting, Li-Shian Jeng, Tzyy-Ming Cheng, Neng-Kuo Chen, Shao-Ta Hsu, Teng-Chun Tsai, Chien-Chung Huang
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Patent number: 7294572Abstract: A method of forming a contact is provided. A substrate having at least two conductive devices is provided. A spacing is located between the two conductive devices. A first dielectric layer is formed over the substrate to cover the two conductive devices and the spacing. A seam is formed in the first dielectric layer within the spacing. Then, a portion of the first dielectric layer is removed to form an opening so that the width of the seam is expanded. A second dielectric layer is formed over the first dielectric layer to fill the opening. A portion of the second dielectric layer and a portion of the first dielectric layer within the spacing are removed until a portion of the surface of the substrate is exposed and a contact opening is formed in the location for forming the contact. Finally, conductive material is deposited to fill the contact opening.Type: GrantFiled: November 24, 2005Date of Patent: November 13, 2007Assignee: United Microelectronics Corp.Inventors: Chao-Lon Yang, Neng-Kuo Chen, Teng-Chun Tsai, Chien-Chung Huang, Shao-Ta Hsu
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Patent number: 7238586Abstract: A seamless trench fill method utilizing ozone-assisted sub-atmospheric pressure chemical vapor deposition (SACVD) technique is provided. After the deposition of a SACVD silicon oxide film, the substrate is subjected to a steam anneal that is performed under H2/O2 environment at a relatively lower temperature ranging between 500° C. and 800° C. for a time period of no less than 30 minutes. The seam defect in the trench is effectively eliminated by this low-temperature steam anneal. To densify the SACVD silicon oxide film, a subsequent N2 anneal is carried out at a higher temperature, for example, 1050° C.Type: GrantFiled: July 21, 2005Date of Patent: July 3, 2007Assignee: United Microelectronics Corp.Inventors: Shao-Ta Hsu, Neng-Kuo Chen, Teng-Chun Tsai
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Publication number: 20070117375Abstract: A method of forming a contact is provided. A substrate having at least two conductive devices is provided. A spacing is located between the two conductive devices. A first dielectric layer is formed over the substrate to cover the two conductive devices and the spacing. A seam is formed in the first dielectric layer within the spacing. Then, a portion of the first dielectric layer is removed to form an opening so that the width of the seam is expanded. A second dielectric layer is formed over the first dielectric layer to fill the opening. A portion of the second dielectric layer and a portion of the first dielectric layer within the spacing are removed until a portion of the surface of the substrate is exposed and a contact opening is formed in the location for forming the contact. Finally, conductive material is deposited to fill the contact opening.Type: ApplicationFiled: November 24, 2005Publication date: May 24, 2007Inventors: Chao-Lon Yang, Neng-Kuo Chen, Teng-Chun Tsai, Chien-Chung Huang, Shao-Ta Hsu
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Patent number: 7205634Abstract: An MIM structure and method for forming the same the method including forming a bottom conductive electrode overlying a semiconducting substrate; forming a first protection layer on the conductive electrode; forming a dielectric layer on the first protection layer; and, forming an upper conductive electrode on the dielectric layer to form a metal-insulator-metal (MIM) structure.Type: GrantFiled: March 10, 2004Date of Patent: April 17, 2007Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Miao-Cheng Liao, Kuo-Hsien Cheng, Cheng-Chao Lin, Shao-Ta Hsu, Ying-Lang Wang
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Publication number: 20070020875Abstract: A seamless trench fill method utilizing ozone-assisted sub-atmospheric pressure chemical vapor deposition (SACVD) technique is provided. After the deposition of a SACVD silicon oxide film, the substrate is subjected to a steam anneal that is performed under H2O2 environment at a relatively lower temperature ranging between 500° C. and 800° C. for a time period of no less than 30 minutes. The seam defect in the trench is effectively eliminated by this low-temperature steam anneal. To densify the SACVD silicon oxide film, a subsequent N2 anneal is carried out at a higher temperature, for example, 1050° C.Type: ApplicationFiled: July 21, 2005Publication date: January 25, 2007Inventors: Shao-Ta Hsu, Neng-Kuo Chen, Teng-Chun Tsai
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Publication number: 20050253268Abstract: A semiconductor interconnect structure including a semiconductor substrate, a semiconductor active device formed in the substrate, a layer of low-k dielectric material, a first patterned conducting layer, a second patterned conducting layer, and a cap layer formed thereon. The low-k material layer is formed over the semiconductor device. The first conducting line is formed in the low-k material layer and connected to the semiconductor active device. The second conducting line is formed in the low-k material layer but not electrically connected to the semiconductor active device. The cap layer is formed over the low-k material layer, the first and second conducting lines. The cap layer includes silicon and carbon.Type: ApplicationFiled: October 15, 2004Publication date: November 17, 2005Inventors: Shao-Ta Hsu, Kuo-Hsien Cheng, Shwang-Ming Jeng, Hung-Tsai Liu, Wei-Cheng Chu, Yu-Ku Lin, Ying-Lang Wang
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Publication number: 20050202616Abstract: An MIM structure and method for forming the same the method including forming a bottom conductive electrode overlying a semiconducting substrate; forming a first protection layer on the conductive electrode; forming a dielectric layer on the first protection layer; and, forming an upper conductive electrode on the dielectric layer to form a metal-insulator-metal (MIM) structure.Type: ApplicationFiled: March 10, 2004Publication date: September 15, 2005Inventors: Miao-Cheng Liao, Kuo-Hsien Cheng, Cheng-Chao Lin, Shao-Ta Hsu, Ying-Lang Wang