Abstract: A sheet input module includes: a tray; a support plate pivotally disposed on the tray to form a first included angle with the tray, wherein the support plate supports multiple sheets; and a sheet-stopper structure being pivotally disposed on the tray and providing a stopping function for the sheets. In an interlocking mode, the sheet-stopper structure is driven by the support plate according to a change of the first included angle and rotated relatively to the tray to adjust a second included angle between a stopping surface of the sheet-stopper structure and the sheets. A printing device using the sheet input module is also provided.

Abstract: Systems and methods for detecting aortic aneurysms using ensemble based deep learning techniques that utilize numerous computed tomography (CT) scans collected from numerous de-identified patients in a database. The system includes software that automates the analysis of a series of CT scans as input (in DICOM file format) and provides output in two dimensions: (1) ranking CT scans by risks of adverse events from aortic aneurysm, (2) providing aortic aneurysm size estimates. A repository of CT scans may be used for training of deep neural networks and additional data may be drawn from localized patient information from institutions and hospitals which grant permission.

Abstract: An electrostatic discharge (ESD) protection device for a semiconductor device that includes a gate, a source including a silicide portion having a plurality of source contacts, and a drain including a silicide portion having a plurality of drain contacts, wherein the source and drain are extended away from the gate along a device axis. The ESD device includes a resist protective oxide (RPO) portion located on the semiconductor device in between the plurality of drain contacts and in between the plurality of source contacts, respectively.

Abstract: An electrostatic discharge (ESD) protection device for a semiconductor device that includes a gate, a source including a silicide portion having a plurality of source contacts, and a drain including a silicide portion having a plurality of drain contacts, wherein the source and drain are extended away from the gate along a device axis. The ESD device includes a resist protective oxide (RPO) portion located on the semiconductor device in between the plurality of drain contacts and in between the plurality of source contacts, respectively.

Abstract: There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.

Abstract: An audio testing system and an audio testing method for an electronic device under test are provided. The audio testing method includes the following steps. A testing audio is sent through a testing audio sending end of a testing device. An electronic device under test is controlled to perform recording through an audio receiving end, so as to generate an under-testing audio. After the recording is completed, the device under test controlled to playback the under-testing audio from one of both-side audio sending ends to perform recording through the testing audio receiving end, and calls an audio analyzing process to generate a first testing result. The device under test controlled to playback the under-testing audio from the other one of the both-side audio sending ends to perform recording through the testing audio receiving end, and calls the audio analyzing process to generate a second testing result.

Abstract: There is provided an integrated circuit includes an output driver and a configurable electrostatic discharging (ESD) power clamp element according to embodiments of the present invention. The output driver includes a first semiconductor element having a first conductivity type and electrically connected to a first power rail; and a second semiconductor element having a second conductivity type different from the first conductivity type and electrically connected to a second power rail. Specifically, the configurable ESD power clamp element is coupled between the first power rail and the second power rail to provide ESD protection when configured in a first hardware state, and forms a portion of the output driver when configured in a second hardware state, thereby increasing the design flexibility of the integrated circuit.

Abstract: An audio testing system and an audio testing method for an electronic device under test are provided. The audio testing method includes the following steps. A testing audio is sent through a testing audio sending end of a testing device. An electronic device under test is controlled to perform recording through an audio receiving end, so as to generate an under-testing audio. After the recording is completed, the device under test controlled to playback the under-testing audio from one of both-side audio sending ends to perform recording through the testing audio receiving end, and calls an audio analyzing process to generate a first testing result. The device under test controlled to playback the under-testing audio from the other one of the both-side audio sending ends to perform recording through the testing audio receiving end, and calls the audio analyzing process to generate a second testing result.

Abstract: A method for testing an audio jack of a portable electronic device is provided. The audio jack has a first sound channel, a second channel and a microphone. First, the first sound channel is controlled to play a designated audio file by the portable electronic device. Nest, the played sound is recorded into another recorded audio file by the portable electronic device at the same when the first sound channel is playing the designated audio file. Afterwards, the recorded audio file is played via the second sound channel by the portable electronic device. Finally, it is determined whether the another recorded audio file that is played matches with the designated audio file, and if the audio files match, it represents that the first sound channel, the second sound channel and the microphone have normal function.

Abstract: An integrated circuit structure includes a semiconductor substrate; a first well region of a first conductivity type over the semiconductor substrate; a second well region of a second conductivity type opposite the first conductivity type encircling the first well region; and a metal-containing layer over and adjoining the first well region and extending over at least an inner portion of the second well region. The metal-containing layer and the first well region form a Schottky barrier. The integrated circuit structure further includes an isolation region encircling the metal-containing layer; and a third well region of the second conductivity type encircling at least a central portion of the first well region. The third well region has a higher impurity concentration than the second well region, and includes a top surface adjoining the metal-containing layer, and a bottom surface higher than bottom surfaces of the first and the second well regions.

Abstract: An integrated light guide plate having axial directional luminance distribution has a substrate. The substrate has a light incident plane, a light emission plane and a bottom surface opposite to the light emission surface. The light incident plane has a plurality of V-cuts formed thereon to serve as prisms. The included angle of the V-cuts is between 85° and 105°. A plurality of pyramidal recesses is formed on the bottom surface of the substrate. Given the formation of the V-cuts and the pyramidal recesses, the integrated light guide plate of the present invention provides an enhanced axial luminous intensity without requiring additional diffuser sheets and prism sheets. Accordingly, the integrated light guide plate has a good directional axial luminance.

Abstract: An electricity output managing system for a fuel cell stack is disclosed. It includes a fuel cell stack, many power switches, an electricity adjusting module, multiple thermal sensors, and a controller. This electricity adjusting module is provided to combine the electricity outputs from these power switches into a single final output. The thermal sensors can detect the inner temperature values of the fuel cell units. The controller can receive the inner temperature values via these thermal sensors and calculate an average of all the inner temperature values which is a floating one. When one of the inner temperature values falls outside a normal range or one of the inner temperature value's variation rates exceeding a preset reference value, the controller turns off the power switch of the corresponding fuel cell unit and sends out a warning signal. So, it can effectuate the fuel cell management by monitoring the inner temperatures of these fuel cell units.

Abstract: An integrated light guide plate having axial directional luminance distribution has a substrate. The substrate has a light incident plane, a light emission plane and a bottom surface opposite to the light emission surface. The light incident plane has a plurality of V-cuts formed thereon to serve as prisms. The included angle of the V-cuts is between 85° and 105°. A plurality of pyramidal recesses is formed on the bottom surface of the substrate. Given the formation of the V-cuts and the pyramidal recesses, the integrated light guide plate of the present invention provides an enhanced axial luminous intensity without requiring additional diffuser sheets and prism sheets. Accordingly, the integrated light guide plate has a good directional axial luminance.

Abstract: A hinge device includes a bearing seat, a spherical joint, a plurality of positioning pins, and a retaining ring. The bearing seat has a containing recess. The spherical joint is rotatably disposed in the containing recess, and the surface of the spherical joint has a plurality of positioning holes. The positioning pins are disposed at the bearing seat and capable of sliding toward or away from the spherical joint. The positioning pins correspond to parts of the positioning holes respectively when the spherical joint rotates to a specific position relative to the bearing seat. The retaining ring is disposed at an opening of the containing recess of the bearing seat and surrounds the positioning pins, the retaining ring is against the positioning pins to allow the positioning pins to be fastened in the corresponding positioning holes when the spherical joint rotates to the specific position relative to the bearing seat.

Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.

Abstract: A high-voltage Schottky diode including a deep P-well having a first width is formed on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.

Abstract: A hinge device includes a bearing seat, a spherical joint, a plurality of positioning pins, and a retaining ring. The bearing seat has a containing recess. The spherical joint is rotatably disposed in the containing recess, and the surface of the spherical joint has a plurality of positioning holes. The positioning pins are disposed at the bearing seat and capable of sliding toward or away from the spherical joint. The positioning pins correspond to parts of the positioning holes respectively when the spherical joint rotates to a specific position relative to the bearing seat. The retaining ring is disposed at an opening of the containing recess of the bearing seat and surrounds the positioning pins, the retaining ring is against the positioning pins to allow the positioning pins to be fastened in the corresponding positioning holes when the spherical joint rotates to the specific position relative to the bearing seat.

Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.

Abstract: A high-voltage Schottky diode including a deep P-well having a first width is fanned on the semiconductor substrate. A doped P-well is disposed over the deep P-well and has a second width that is less than the width of the deep P-well. An M-type guard ring is formed around the upper surface of the second doped well, A Schottky metal is disposed on an upper surface of the second doped well and the N-type guard ring.

Abstract: A transistor suitable for high-voltage applications is provided. The transistor is formed on a substrate having a deep well of a first conductivity type. A first well of the first conductivity type and a second well of a second conductivity type are formed such that they are not immediately adjacent each other. The well of the first conductivity type and the second conductivity type may be formed simultaneously as respective wells for low-voltage devices. In this manner, the high-voltage devices may be formed on the same wafer as low-voltage devices with fewer process steps, thereby reducing costs and process time. A doped isolation well may be formed adjacent the first well on an opposing side from the second well to provide further device isolation.