Patents by Inventor Shao-Ting WU

Shao-Ting WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12241157
    Abstract: A system and method for cleaning a preclean process chamber in between wafer processing. The internal pressure of the preclean process chamber is reduced to a first pressure and a first gas that consists of oxygen and an inert or noble gas, is introduced into the chamber. Plasma is generated within the preclean process chamber using the first gas at the first pressure. Internal pressure is then reduced to a second pressure, less than the first, and the first gas is continued into the chamber. Plasma is then generated using the first gas at the second pressure. Thereafter, a second gas, consisting of an oxygen-free inert or noble gas, is introduced into the chamber at the second pressure, following which plasma is generated within the chamber using only the second gas.
    Type: Grant
    Filed: February 24, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Ting Tsai, Hung-Chih Wang, Hong-Ming Lo, Shao-Shuo Wu, Su-Yu Yeh
  • Publication number: 20250071986
    Abstract: A memory device is disclosed. The memory device includes a memory array comprising a plurality of memory cells. At least a first one of the memory cells, by default, permanently presents a first logic state based on a short circuit. At least a second one of the memory cells, by default, permanently presents a second logic state opposite to the first logic state based on an open circuit.
    Type: Application
    Filed: November 24, 2023
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shao-Ting Wu, Meng-Sheng Chang
  • Patent number: 12237264
    Abstract: A fusible structure includes: a metal line in a first metal layer extending along a first direction; and a first dummy structure disposed proximal to the metal line relative to a second direction, the second direction being perpendicular to the first direction, the first dummy structure being in a second metal layer. Relative to the first direction, the metal line includes first, second and third portions, the second portion being between the first portion and third portion. Relative to a third direction that is perpendicular to the first direction and the second direction, the first portion has a first thickness and the second portion has a second thickness, the first thickness being greater than the second thickness.
    Type: Grant
    Filed: May 23, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Ting Wu, Meng-Sheng Chang, Shao-Yu Chou, Chung-I Huang
  • Patent number: 12205891
    Abstract: A method (fabricating a fusible structure) includes forming a metal line that extends in a first direction, the forming a metal line including: configuring the mask such that the metal line has a first portion that is between a second portion and a third portion; and using an optical proximity correction technique with a mask so that the first portion has a first thickness that is thinner than a second thickness of each of the second portion and the third portion; and forming a first dummy structure proximal to the metal line and aligned with the first portion relative to the first direction.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: January 21, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Ting Wu, Meng-Sheng Chang, Shao-Yu Chou, Chung-I Huang
  • Patent number: 12190949
    Abstract: A memory circuit includes a bias voltage generator including a first buffer configured to generate a first bias voltage based on a reference voltage and a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage. The memory circuit includes a plurality of voltage clamp devices coupled to the plurality of second buffers, and each voltage clamp device is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages.
    Type: Grant
    Filed: May 12, 2023
    Date of Patent: January 7, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Perng-Fei Yuh, Shao-Ting Wu, Yu-Fan Lin
  • Publication number: 20240147711
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: PERNG-FEI YUH, YIH WANG, MENG-SHENG CHANG, JUI-CHE TSAI, KU-FENG LIN, YU-WEI LIN, KEH-JENG CHANG, CHANSYUN DAVID YANG, SHAO-TING WU, SHAO-YU CHOU, PHILEX MING-YAN FAN, YOSHITAKA YAMAUCHI, TZU-HSIEN YANG
  • Patent number: 11903188
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Grant
    Filed: February 16, 2022
    Date of Patent: February 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Perng-Fei Yuh, Yih Wang, Meng-Sheng Chang, Jui-Che Tsai, Ku-Feng Lin, Yu-Wei Lin, Keh-Jeng Chang, Chansyun David Yang, Shao-Ting Wu, Shao-Yu Chou, Philex Ming-Yan Fan, Yoshitaka Yamauchi, Tzu-Hsien Yang
  • Publication number: 20230298995
    Abstract: A fusible structure includes: a metal line in a first metal layer extending along a first direction; and a first dummy structure disposed proximal to the metal line relative to a second direction, the second direction being perpendicular to the first direction, the first dummy structure being in a second metal layer. Relative to the first direction, the metal line includes first, second and third portions, the second portion being between the first portion and third portion. Relative to a third direction that is perpendicular to the first direction and the second direction, the first portion has a first thickness and the second portion has a second thickness, the first thickness being greater than the second thickness.
    Type: Application
    Filed: May 23, 2023
    Publication date: September 21, 2023
    Inventors: Shao-Ting WU, Meng-Sheng CHANG, Shao-Yu CHOU, Chung-I HUANG
  • Publication number: 20230282278
    Abstract: A memory circuit includes a bias voltage generator including a first buffer configured to generate a first bias voltage based on a reference voltage and a plurality of second buffers configured to generate a plurality of second bias voltages based on the first bias voltage. The memory circuit includes a plurality of voltage clamp devices coupled to the plurality of second buffers, and each voltage clamp device is configured to apply a drive voltage to a corresponding resistance-based memory device of a plurality of resistance-based memory devices based on the corresponding second bias voltage of the plurality of second bias voltages.
    Type: Application
    Filed: May 12, 2023
    Publication date: September 7, 2023
    Inventors: Perng-Fei YUH, Shao-Ting WU, Yu-Fan LIN
  • Publication number: 20230262969
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Application
    Filed: February 16, 2022
    Publication date: August 17, 2023
    Inventors: PERNG-FEI YUH, YIH WANG, MENG-SHENG CHANG, JUI-CHE TSAI, KU-FENG LIN, YU-WEI LIN, KEH-JENG CHANG, CHANSYUN DAVID YANG, SHAO-TING WU, SHAO-YU CHOU, PHILEX MING-YAN FAN, YOSHITAKA YAMAUCHI, TZU-HSIEN YANG
  • Patent number: 11658114
    Abstract: A fusible structure includes a metal line with different portions having different thicknesses. Thinner portions of the metal line are designed to be destructively altered at lower voltages while thicker portions of the metal line are designed to be destructively altered at lower voltages. Furthermore, one or more dummy structures are disposed proximal to the thinner portions of the metal line. In some embodiments, dummy structures are placed with sufficient proximity so as to protect against metal sputtering when metal line is destructively altered.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: May 23, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shao-Ting Wu, Meng-Sheng Chang, Shao-Yu Chou, Chung-I Huang
  • Patent number: 11651819
    Abstract: A bias voltage generator includes a first current path, a first voltage clamp device, and a first buffer. The bias voltage generator receives a reference voltage and generates a first bias voltage based on a voltage difference between the reference voltage and a first drive voltage, the first voltage clamp device generates the first drive voltage based on the first bias voltage by applying the first drive voltage to the first current path, and the first buffer receives the first bias voltage and generates a second bias voltage based on the first bias voltage. A second current path includes a resistance-based memory device, and a second voltage clamp device generates a second drive voltage based on the second bias voltage and applies the second drive voltage to the second current path.
    Type: Grant
    Filed: March 23, 2021
    Date of Patent: May 16, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Perng-Fei Yuh, Shao-Ting Wu, Yu-Fan Lin
  • Publication number: 20220384339
    Abstract: A method (fabricating a fusible structure) includes forming a metal line that extends in a first direction, the forming a metal line including: configuring the mask such that the metal line has a first portion that is between a second portion and a third portion; and using an optical proximity correction technique with a mask so that the first portion has a first thickness that is thinner than a second thickness of each of the second portion and the third portion; and forming a first dummy structure proximal to the metal line and aligned with the first portion relative to the first direction.
    Type: Application
    Filed: August 10, 2022
    Publication date: December 1, 2022
    Inventors: Shao-Ting WU, Meng-Sheng CHANG, Shao-Yu CHOU, Chung-I HUANG
  • Publication number: 20220122914
    Abstract: A fusible structure includes a metal line with different portions having different thicknesses. Thinner portions of the metal line are designed to be destructively altered at lower voltages while thicker portions of the metal line are designed to be destructively altered at lower voltages. Furthermore, one or more dummy structures are disposed proximal to the thinner portions of the metal line. In some embodiments, dummy structures are placed with sufficient proximity so as to protect against metal sputtering when metal line is destructively altered.
    Type: Application
    Filed: April 13, 2021
    Publication date: April 21, 2022
    Inventors: Shao-Ting WU, Meng-Sheng CHANG, Shao-Yu CHOU, Chung-I HUANG
  • Publication number: 20220028453
    Abstract: A bias voltage generator includes a first current path, a first voltage clamp device, and a first buffer. The bias voltage generator receives a reference voltage and generates a first bias voltage based on a voltage difference between the reference voltage and a first drive voltage, the first voltage clamp device generates the first drive voltage based on the first bias voltage by applying the first drive voltage to the first current path, and the first buffer receives the first bias voltage and generates a second bias voltage based on the first bias voltage. A second current path includes a resistance-based memory device, and a second voltage clamp device generates a second drive voltage based on the second bias voltage and applies the second drive voltage to the second current path.
    Type: Application
    Filed: March 23, 2021
    Publication date: January 27, 2022
    Inventors: Perng-Fei YUH, Shao-Ting WU, Yu-Fan LIN