Patents by Inventor Shao W. Pan

Shao W. Pan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5629884
    Abstract: A digital log converter is provided which includes a comparator (10) and a log signal generator (20). Upon receiving a digital input signal (12), the comparator (10) determines whether an upper bit-slice of the input signal (12) equals zero. If the upper bit-slice is zero, the log signal generator (20) subtracts an offset from at least one parameter to generate a log signal (16); otherwise, the log signal generator (20) interpolates the at least one parameter and a lower bit-slice of the input signal (12) to generate the log signal (16).
    Type: Grant
    Filed: July 28, 1995
    Date of Patent: May 13, 1997
    Assignee: Motorola, Inc.
    Inventors: Shao W. Pan, Shay-Ping T. Wang
  • Patent number: 5612899
    Abstract: A video signal is converted into compressed frame signals, each comprising a coefficient signal of block coefficient signals for each frame in a video image. Each of the block coefficient signals represents the pixels in a pixel map block (420) with the coefficients in a hybrid polynomial. The hybrid polynomial contains discrete cosine terms, a constant term separated from the discrete cosine terms, and polynomial terms extracted from the discrete cosine terms. Each block coefficient signal contains a background component representing a coefficient of the constant term, a linear component representing the coefficients of the polynomial terms, and a nonlinear component representing the coefficients of the discrete cosine terms.
    Type: Grant
    Filed: June 27, 1995
    Date of Patent: March 18, 1997
    Assignee: Motorola, Inc.
    Inventors: Shao W. Pan, Shay-Ping T. Wang, Nicholas M. Labun
  • Patent number: 5553012
    Abstract: A circuit and method for computing an exponential signal x.sup.g is provided. The circuit includes a logarithm converter which converts an input signal to binary word that represents the logarithm of an input signal x. A first shift register shifts the binary word in a bit-wise fashion to produce a first intermediate value; while a second shift register shifts the binary word in a bit-wise fashion to produce a second intermediate value. The shift registers may be implemented using multiplexers. The shifting operations are equivalent to multiplying the intermediate values by a factor which is a power of two. The first intermediate value is either added to or subtracted from the second intermediate value to produce a combined value. An inverse-logarithm converter converts the combined value to the exponential signal.
    Type: Grant
    Filed: March 10, 1995
    Date of Patent: September 3, 1996
    Assignee: Motorola, Inc.
    Inventors: John M. Buss, James D. Dworkin, Scott E. Lloyd, Shao W. Pan, Stephen L. Smith, Shay-Ping T. Wang