Patents by Inventor Shao Wang

Shao Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250113517
    Abstract: A method of forming source/drain regions of semiconductor devices is disclosed. The method includes forming a fin structure on a substrate, forming a polysilicon structure on the fin structure, removing a portion of the fin structure adjacent to the polysilicon structure to form an opening, and forming a S/D region in the opening. The forming the S/D region includes exposing the fin structure in the opening to a first flow rate of a precursor gas during a first phase of a gas flow cycle, a second flow rate of the precursor gas during a second phase of the gas flow cycle. The exposing the fin structure in the opening to the precursor gas, the etching gas, and the plasma is performed in an in-situ process.
    Type: Application
    Filed: September 29, 2023
    Publication date: April 3, 2025
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shao-An WANG, Ding-Kang SHIH, Chia-Ling PAI, Pinyen LIN
  • Publication number: 20250006742
    Abstract: A semiconductor device that has two transistors and a source/drain contact. The first transistor has a layer of semiconductor material that acts as a channel, a structure that serves as a gate and wraps around the semiconductor channel layer, and two epitaxy structures on either end of the semiconductor channel layer that function as the source and drain. The second transistor is situated above the first transistor and has similar components, including a semiconductor channel layer, gate structure, and source/drain epitaxy structures. The connection between the first and second source/drain epitaxy structures is made by a source/drain contact that passes through one of the second source/drain epitaxy structures. This contact is made up of a metal plug and a metal liner that lines the plug.
    Type: Application
    Filed: July 1, 2023
    Publication date: January 2, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yuting CHENG, Tzu Pei CHEN, Kuan-Kan HU, Shao-An WANG, Jung-Hao CHANG, Sung-Li WANG
  • Publication number: 20240332091
    Abstract: A semiconductor device and a method of fabricating the semiconductor device are disclosed. The method includes forming nanostructured channel regions, forming gate openings surrounding the nanostructured channel regions, forming oxide layers on exposed surfaces of the nanostructured channel regions in the gate openings, depositing a diffusion barrier layer on the oxide layers, depositing a first dielectric layer on the diffusion barrier layer, performing a doping process on the diffusion barrier layer and the first dielectric layer to form a doped diffusion barrier layer and a doped dielectric layer, and depositing a conductive layer on the doped dielectric layer.
    Type: Application
    Filed: March 29, 2023
    Publication date: October 3, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shen-Yang LEE, Hsiang-Pi Chang, Huiching Chang, Shao An Wang, Kenichi Sano, Huang-Lin Chao
  • Publication number: 20240006229
    Abstract: A method for filling a gap in a semiconductor structure includes: forming the gap between two raised portions of the semiconductor structure, the gap having a bottom surface and two lateral surfaces each extending upwardly from the bottom surface along one of the raised portions to terminate at an upper surface of a corresponding one of the raised portions; and forming a filler element in the gap in a bottom-up manner that avoids the filler element being formed laterally.
    Type: Application
    Filed: June 30, 2022
    Publication date: January 4, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yi-Hsiu CHEN, Shao-An WANG, Kenichi SANO, Andrew Joseph KELLY
  • Publication number: 20230253308
    Abstract: A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.
    Type: Application
    Filed: February 10, 2022
    Publication date: August 10, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chia-Hung CHU, Po-Chin CHANG, Tzu-Pei CHEN, Yuting CHENG, Kan-Ju LIN, Chih-Shiun CHOU, Hung-Yi HUANG, Pinyen LIN, Sung-Li WANG, Sheng-Tsung WANG, Lin-Yu HUANG, Shao-An WANG, Harry CHIEN
  • Patent number: D576261
    Type: Grant
    Filed: October 10, 2006
    Date of Patent: September 2, 2008
    Inventor: Shao Wang
  • Patent number: D603188
    Type: Grant
    Filed: February 2, 2009
    Date of Patent: November 3, 2009
    Inventor: Shao Wang
  • Patent number: D609498
    Type: Grant
    Filed: August 29, 2009
    Date of Patent: February 9, 2010
    Inventor: Shao Wang
  • Patent number: D653735
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: February 7, 2012
    Inventor: Shao Wang
  • Patent number: D947627
    Type: Grant
    Filed: May 19, 2021
    Date of Patent: April 5, 2022
    Inventor: Shao Wang
  • Patent number: D960404
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: August 9, 2022
    Inventor: Shao Wang
  • Patent number: D980464
    Type: Grant
    Filed: October 17, 2021
    Date of Patent: March 7, 2023
    Inventor: Shao Wang