Patents by Inventor Shao-Wei Feng

Shao-Wei Feng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190371916
    Abstract: A semiconductor structure having a metal gate includes a dielectric layer. The dielectric layer having a recess is disposed on a substrate, wherein the dielectric layer has a top part and a bottom part, and the tensile stress of the top part is larger than the tensile stress of the bottom part, thereby the recess having a sidewall profile tapering from bottom to top. The present invention also provides a method of forming said semiconductor structure.
    Type: Application
    Filed: June 26, 2018
    Publication date: December 5, 2019
    Inventors: Jing-Yi Lin, Yi-Wen Chen, Hung-Yi Wu, Ping-Wei Huang, Shao-Wei Wang, Yueh-Chi Chuang, Hung-Jen Huang, Hao-Che Feng
  • Patent number: 10418435
    Abstract: A pixel structure including a substrate, a power wire, a planarization layer, a drive circuit and a conductive structure is provided. The substrate has a layout area and a light-transmitting area located outside the layout area. The power wire is disposed on the layout area of the substrate. The power wire includes a shielding layer. The planarization layer is disposed on the substrate and covers the power wire. The drive circuit is disposed on the planarization layer and corresponds to the layout area. The drive circuit includes a first active device. The shielding layer overlaps with the first active device. The conductive structure is disposed in the planarization layer and distributed corresponding to the layout area. The power wire is electrically connected with the drive circuit through the conductive structure. A display panel is also provided.
    Type: Grant
    Filed: August 31, 2017
    Date of Patent: September 17, 2019
    Assignees: Industrial Technology Research Institute, Intellectual Property Innovation Corporation
    Inventors: Tai-Jui Wang, Chieh-Wei Feng, Meng-Jung Yang, Wei-Han Chen, Shao-An Yan, Tsu-Chiang Chang
  • Patent number: 9966986
    Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: May 8, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shih-Chi Shen, Shao-Wei Feng, Chun-Ming Kuo, Chi-Hsueh Wang, Ang-Sheng Lin
  • Patent number: 9867135
    Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a reference clock signal processor. The frequency synthesizer circuit receives a processed reference clock signal and generates a radio-frequency clock signal according to the processed reference clock signal. The reference clock signal processor receives an original reference clock signal from an oscillator and processes the original reference clock signal according to an indication signal to generate the processed reference clock signal. The indication signal is generated according to a required reference clock frequency of a communications apparatus. When the required reference clock frequency is high, a frequency of the processed reference clock signal is a multiple of a frequency of the original reference clock signal, and when the required reference clock frequency is low, the frequency of the original reference clock signal is a multiple of the frequency of the processed reference clock signal.
    Type: Grant
    Filed: February 6, 2017
    Date of Patent: January 9, 2018
    Assignee: MEDIATEK INC.
    Inventors: Shao-Wei Feng, Shih-Chi Shen, Tso-Mo Chen, Chun-Ming Kuo
  • Patent number: 9065690
    Abstract: A method for performing channel shortening equalization with frequency notch mitigation is provided, where the method is applied to an electronic device. The method includes: obtaining channel response information from channel estimation to determine a relaxed channel convolution matrix corresponding to the channel response information, with the relaxed channel convolution matrix being a partial matrix of a channel convolution matrix corresponding to the channel response information, wherein the relaxed channel convolution matrix is obtained from omitting a portion of matrix elements of the channel convolution matrix; and based upon the relaxed channel convolution matrix, jointly performing time domain channel shortening control and frequency domain flatness control over the TEQ to perform channel shortening equalization with frequency notch mitigation by utilizing the TEQ. In particular, the portion of matrix elements includes a plurality of rows of matrix elements within the channel convolution matrix.
    Type: Grant
    Filed: May 1, 2012
    Date of Patent: June 23, 2015
    Assignees: MEDIATEK INC., National Taiwan University
    Inventors: Yen-Liang Chen, Shao-Wei Feng, Cheng-Zhou Zhan, An-Yeu Wu
  • Publication number: 20130114664
    Abstract: A method for performing channel shortening equalization with frequency notch mitigation is provided, where the method is applied to an electronic device. The method includes: obtaining channel response information from channel estimation to determine a relaxed channel convolution matrix corresponding to the channel response information, with the relaxed channel convolution matrix being a partial matrix of a channel convolution matrix corresponding to the channel response information, wherein the relaxed channel convolution matrix is obtained from omitting a portion of matrix elements of the channel convolution matrix; and based upon the relaxed channel convolution matrix, jointly performing time domain channel shortening control and frequency domain flatness control over the TEQ to perform channel shortening equalization with frequency notch mitigation by utilizing the TEQ. In particular, the portion of matrix elements includes a plurality of rows of matrix elements within the channel convolution matrix.
    Type: Application
    Filed: May 1, 2012
    Publication date: May 9, 2013
    Inventors: Yen-Liang Chen, Shao-Wei Feng, Cheng-Zhou Zhan, An-Yeu Wu