Patents by Inventor Shao-Wei Lin

Shao-Wei Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240144305
    Abstract: A method for allocating perishable products based on machine learning, includes using a sales estimation model to evaluate estimated sales of a plurality of perishable products in a predetermined period, using a rating model to calculate a predetermined rate of the plurality of perishable products in the predetermined period according to the estimated sales, using an allocation model to adjust an allocation ratio of the plurality of perishable products in a plurality of marketing channels according to the estimated sales and the predetermined rate if a current rate is lower than the predetermined rate, and determining the numbers of perishable products allocated to the plurality of marketing channels according to the allocation ratio.
    Type: Application
    Filed: December 27, 2022
    Publication date: May 2, 2024
    Applicant: DUN-QIAN Intelligent Technology Co., Ltd.
    Inventors: Yen-Chu Chen, Ling-Jung Lin, Shao-Chen Liu, Hsuan-Wei Chen, Shuh-Shian Tsai
  • Publication number: 20240147711
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: PERNG-FEI YUH, YIH WANG, MENG-SHENG CHANG, JUI-CHE TSAI, KU-FENG LIN, YU-WEI LIN, KEH-JENG CHANG, CHANSYUN DAVID YANG, SHAO-TING WU, SHAO-YU CHOU, PHILEX MING-YAN FAN, YOSHITAKA YAMAUCHI, TZU-HSIEN YANG
  • Publication number: 20240119473
    Abstract: A rate adjustment method includes a rate estimation model generating a plurality of estimated rates according to a plurality of training data, a revenue estimation model generating an estimated revenue according to the plurality of estimated rates, updating the rate estimation model according to the estimated revenue to generate an updated rate estimation model, and inputting a plurality of current data into the updated rate estimation model to update the plurality of estimated rates.
    Type: Application
    Filed: December 27, 2022
    Publication date: April 11, 2024
    Applicant: DUN-QIAN Intelligent Technology Co., Ltd.
    Inventors: Yen-Chu Chen, Ling-Jung Lin, Shao-Chen Liu, Hsuan-Wei Chen, Shuh-Shian Tsai
  • Publication number: 20240113112
    Abstract: Methods of cutting gate structures and fins, and structures formed thereby, are described. In an embodiment, a substrate includes first and second fins and an isolation region. The first and second fins extend longitudinally parallel, with the isolation region disposed therebetween. A gate structure includes a conformal gate dielectric over the first fin and a gate electrode over the conformal gate dielectric. A first insulating fill structure abuts the gate structure and extends vertically from a level of an upper surface of the gate structure to at least a surface of the isolation region. No portion of the conformal gate dielectric extends vertically between the first insulating fill structure and the gate electrode. A second insulating fill structure abuts the first insulating fill structure and an end sidewall of the second fin. The first insulating fill structure is disposed laterally between the gate structure and the second insulating fill structure.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Ryan Chia-Jen Chen, Cheng-Chung Chang, Shao-Hua Hsu, Yu-Hsien Lin, Ming-Ching Chang, Li-Wei Yin, Tzu-Wen Pan, Yi-Chun Chen
  • Patent number: 11940828
    Abstract: A voltage tracking circuit is provided. The voltage tracking circuit includes first and second P-type transistors and a control circuit. The drain of the first P-type transistor is coupled to a first voltage terminal. The gate and the drain of the second P-type transistor are respectively coupled to the first voltage terminal and a second voltage terminal. The control circuit is coupled to the first and second voltage terminals and generates a control voltage according to the first voltage and the second voltage. The sources of the first and second P-type transistors are coupled to an output terminal of the voltage tracking circuit, and the output voltage is generated at the output terminal. In response to the second voltage being higher than the first voltage, the control circuit generates the control signal to turn off the first P-type transistor.
    Type: Grant
    Filed: August 17, 2022
    Date of Patent: March 26, 2024
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shao-Chang Huang, Yeh-Ning Jou, Ching-Ho Li, Kai-Chieh Hsu, Chun-Chih Chen, Chien-Wei Wang, Gong-Kai Lin, Li-Fan Chen
  • Patent number: 8037586
    Abstract: A method for fabricating a blind via structure of a substrate is provided. First, a substrate is provided, which includes a conductive layer, a metal layer, and a dielectric layer disposed between the conductive layer and the metal layer. Next, a cover layer is formed on the conductive layer. Finally, the substrate formed with the cover layer is irradiated by a laser beam to form at least one blind via structure extending from the cover layer to the metal layer. The blind via structure includes a first opening, a second opening, and a third opening linking to one another. The first opening passes through the cover layer. The second opening passes through the conductive layer. The third opening passes through the dielectric layer. For example, a size of the first opening is greater than a size of the second opening and a size of the third opening.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: October 18, 2011
    Assignee: Unimicron Technology Corp.
    Inventors: Wei-Ming Cheng, Shao-Wei Lin, Pao-Chin Chen
  • Publication number: 20100031502
    Abstract: A method for fabricating a blind via structure of a substrate is provided. First, a substrate is provided, which includes a conductive layer, a metal layer, and a dielectric layer disposed between the conductive layer and the metal layer. Next, a cover layer is formed on the conductive layer. Finally, the substrate formed with the cover layer is irradiated by a laser beam to form at least one blind via structure extending from the cover layer to the metal layer. The blind via structure includes a first opening, a second opening, and a third opening linking to one another. The first opening passes through the cover layer. The second opening passes through the conductive layer. The third opening passes through the dielectric layer. For example, a size of the first opening is greater than a size of the second opening and a size of the third opening.
    Type: Application
    Filed: October 28, 2008
    Publication date: February 11, 2010
    Applicant: UNIMICRON TECHNOLOGY CORP.
    Inventors: Wei-Ming Cheng, Shao-Wei Lin, Pao-Chin Chen