Abstract: A chip structure with solder bumps and the method for producing the same are disclosed. The chip structure with solder bumps includes a chip, a plurality of pads arranged on one surface of the chip, a protection layer formed on the surface of the chip and exposing the pads, a first photo-imaginable dielectric layer covered on the protection layer, a plurality of UBMs arranged on the pads, and extends over the first photo-imaginable dielectric layer respectively, a second photo-imaginable dielectric layer covered on the UBMs and the first photo-imaginable dielectric layer, and a plurality of conductive bumps relative to the pads and disposed on the UBMs respectively. Each UBM has a heat-dissipation portion extending to the edge of the surface of the chip. The second photo-imaginable dielectric layer reveals the heat-dissipation portions respectively.

Abstract: A chip structure comprising a substrate, a circuitry unit, a plurality of bonding pads, a first passivation layer and a redistribution layer is provided. The circuitry unit is disposed on the substrate, and the bonding pads are disposed on the circuitry unit. Moreover, the first passivation layer is disposed on the circuitry unit and exposes the bonding pads. The redistribution layer of a Ti/Cu/Ti multi-layered structure is disposed on the first passivation layer, and is electrically connected with the bonding pads. In addition, the redistribution layer of a Ti/Cu/Ti multi-layered structure has excellent conductivity such that electrical characteristics of the chip structure are enhanced effectively.

Abstract: A chip structure and the manufacturing process thereof are provided. The feature of the present application is that the chip structure has a first passivation layer covering a substrate of the chip and exposing each of bonding pads and a portion of the substrate surface, and a second passivation layer covering the sidewalls of the first passivation layer and the portion of substrate surface exposed by the first passivation layer, to prevent moisture infiltration from the edge of the substrate. Therefore, the reliability of the chip structure is enhanced.