Patents by Inventor SHAO-YU CHANG

SHAO-YU CHANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12010833
    Abstract: A memory device includes a first memory cell having a first polysilicon line associated with a first read word line and intersecting a first active region and a second active region, and a second polysilicon line and a first CPODE associated with a first program word line, the second polysilicon line intersecting the first active region and the first CPODE intersecting the second active region. The memory device also includes a second memory cell adjacent to the first memory cell, the second memory cell having a third polysilicon line associated with a second read word line and intersecting the first active region and the second active region, and a fourth polysilicon line and a second CPODE associated with a second program word line, the fourth polysilicon line intersecting the second active region and the second CPODE intersecting the first active region to form a cross-arrangement of CPODE.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: June 11, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Meng-Sheng Chang, Chia-En Huang, Shao-Yu Chou, Yih Wang
  • Publication number: 20240146305
    Abstract: The present disclosure includes a voltage provision circuit. In one aspect of the present disclosure, a voltage provision circuit is disclosed. The voltage provision circuit includes a first NMOS transistor gated with a first control signal and sourced with a ground voltage. The voltage provision circuit includes a second NMOS transistor gated with a second control signal complementary to the first control signal and sourced with the ground voltage. The voltage provision circuit includes a first PMOS transistor sourced with a first supply voltage. The voltage provision circuit includes a second PMOS transistor sourced with the first supply voltage. The voltage provision circuit includes a voltage modulation circuit, coupled between the first to second PMOS transistors and the first to second NMOS transistors, that is configured to provide a first intermediate signal based on the first and second control signals.
    Type: Application
    Filed: February 16, 2023
    Publication date: May 2, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Yu Yu, Meng-Sheng Chang, Shao-Yu Chou
  • Publication number: 20240147711
    Abstract: The present disclosure provides a memory device, a semiconductor device, and a method of operating a memory device. A memory device includes a memory cell, a bit line, a word line, a select transistor, a fuse element, and a heater. The bit line is connected to the memory cell. The word line is connected to the memory cell. The select transistor is disposed in the memory cell. A gate of the select transistor is connected to the word line. The fuse element is disposed in the memory cell. The fuse element is connected to the bit line and the select transistor. The heater is configured to heat the fuse element.
    Type: Application
    Filed: January 4, 2024
    Publication date: May 2, 2024
    Inventors: PERNG-FEI YUH, YIH WANG, MENG-SHENG CHANG, JUI-CHE TSAI, KU-FENG LIN, YU-WEI LIN, KEH-JENG CHANG, CHANSYUN DAVID YANG, SHAO-TING WU, SHAO-YU CHOU, PHILEX MING-YAN FAN, YOSHITAKA YAMAUCHI, TZU-HSIEN YANG
  • Publication number: 20240096431
    Abstract: A memory circuit includes a non-volatile memory cell, a comparator and a detection circuit. The comparator is coupled to the non-volatile memory cell, and configured to generate a first output signal. The comparator including a first input terminal and a first output terminal. The first input terminal is coupled to the non-volatile memory cell by a first node, and configured to receive a first voltage. The first output terminal is configured to output the first output signal. The detection circuit is coupled to the comparator and the non-volatile memory cell. The detection circuit is configured to latch the first output signal and disrupt a current path between at least the non-volatile memory cell and the comparator. The detection circuit includes a first inverter coupled to the first output terminal of the comparator and configured to generate an inverted first output signal.
    Type: Application
    Filed: November 29, 2023
    Publication date: March 21, 2024
    Inventors: Chun-Hao CHANG, Gu-Huan LI, Shao-Yu CHOU
  • Publication number: 20240071537
    Abstract: A multi-fuse memory cell is disclosed. The circuit includes: a first fuse element electrically coupled to a first transistor, a gate of the first transistor is electrically coupled to a first selection signal; a second fuse element electrically coupled to a second transistor, a gate of the second transistor is electrically coupled to a second selection signal, both the first transistor and the second transistor are grounded; and a programming transistor electrically coupled to the first fuse element and the second fuse element, wherein a gate of the programming transistor is electrically coupled to a programming signal.
    Type: Application
    Filed: November 7, 2023
    Publication date: February 29, 2024
    Inventors: Meng-Sheng Chang, Chia-En Huang, Shao-Yu Chou, Yih Wang
  • Publication number: 20230375804
    Abstract: An imaging optical lens assembly includes five optical elements with refractive power. The five optical elements, in order from an object side to an image side along an optical path, are a first optical element, a second optical element, a third optical element, a fourth optical element, and a fifth optical element. The first optical element has an object-side surface being concave in a paraxial region thereof. The third optical element has negative refractive power.
    Type: Application
    Filed: July 17, 2023
    Publication date: November 23, 2023
    Inventors: SHAO-YU CHANG, WEI-YU CHEN
  • Patent number: 11747590
    Abstract: An imaging optical lens assembly includes five optical elements with refractive power. The five optical elements, in order from an object side to an image side along an optical path, are a first optical element, a second optical element, a third optical element, a fourth optical element, and a fifth optical element. The first optical element has an object-side surface being concave in a paraxial region thereof. The third optical element has negative refractive power.
    Type: Grant
    Filed: September 3, 2020
    Date of Patent: September 5, 2023
    Assignee: LARGAN PRECISION CO., LTD.
    Inventors: Shao-Yu Chang, Wei-Yu Chen
  • Publication number: 20220268571
    Abstract: A depth detection apparatus includes: an emitting assembly for emitting a speckle light signal to a detection object, where the emitting assembly is configured to cause the speckle light signal to generate positive distortion; an imaging lens for imaging, to a photoelectric sensor, a depth light signal returned after the speckle light signal strikes the detection object, wherein the imaging lens is configured to cause the imaging of the depth light signal to generate negative distortion; and a photoelectric sensor for converting the depth light signal into an electrical signal, wherein a difference between an absolute value of a distortion amount of the negative distortion and an absolute value of a distortion amount of the positive distortion does not exceed 0.05, and the negative distortion and the positive distortion each are distortion having a distortion amount whose absolute value is greater than or equal to 0.03.
    Type: Application
    Filed: September 28, 2021
    Publication date: August 25, 2022
    Applicant: DIXTECH INNOVATION PTE. LTD.
    Inventors: Fei Hsin TSAI, Shao Yu CHANG, Cong GE
  • Publication number: 20210341707
    Abstract: An imaging optical lens assembly includes five optical elements with refractive power. The five optical elements, in order from an object side to an image side along an optical path, are a first optical element, a second optical element, a third optical element, a fourth optical element, and a fifth optical element. The first optical element has an object-side surface being concave in a paraxial region thereof. The third optical element has negative refractive power.
    Type: Application
    Filed: September 3, 2020
    Publication date: November 4, 2021
    Inventors: SHAO-YU CHANG, WEI-YU CHEN