Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: A built-in self-tester (BIST) of a semiconductor device including: an input/output (I/O) circuit including an output buffer and an input buffer, an output of the output buffer being coupled at an I/O terminal to an input of the input buffer, the I/O terminal being configured to receive or provide an external I/O signal; one or more resistive-network cell regions arranged to affect a reference current received at the I/O terminal; and a switching arrangement configured to selectively couple the one or more resistive-network cell regions alternatively to a first reference voltage during a first phase or a second reference voltage during a second phase, the switching arrangement being further configured to determine electrostatic discharge (ESD) damage to metal-oxide-semiconductor (MOS) transistors included in the semiconductor device based on (1) phase and (2) an output signal of the input buffer

Abstract: The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.

Abstract: The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

Abstract: The present disclosure provides a crack detection unit (CDU), a semiconductor die, and a method of detecting a crack of a semiconductor die. The CDU comprises a switching circuit, a crack sensor, and a logic circuit. The switching circuit is configured to enable the crack sensor. The crack sensor is configured to be electrically connected to the switching circuit, the ground, and an operating voltage. The logic circuit is configured to be electrically connected to the switching circuit and the crack sensor, wherein the CDU is enabled based on an input of the logic circuit. The output of the logic circuit indicates whether the crack sensor contains a crack.

Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a MOS transistor. A first source/drain region of the MOS transistor may be connected to the die-to-die interconnect.

Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a PMOS transistor and an NMOS transistor. A first source/drain region of the PMOS transistor may be connected to a first source/drain region of the NMOS transistor and the die-to-die interconnect.

Abstract: A circuit includes a voltage divider circuit configured to generate a feedback voltage according to an output voltage, an operational amplifier configured to output a driving signal according to the feedback voltage and a reference voltage and a pass gate circuit including multiple current paths. The current paths are controlled by the driving signal and connected in parallel between the voltage divider circuit and a power reference node.

Abstract: In some embodiments, digital logic components, such as those found in standard cells in integrated circuit devices, are used to synthesize signals with controllable waveforms that result in transmitted signals that meet certain requirements, such as above-threshold high openings and below-threshold over/under-shooting. In some embodiments, driving buffers with logic controls and delay chains are used to achieve controllable slew rates at rising and falling edges to minimize over/under shooting behavior in signals. In some embodiments, control logic and delay chains produce controllable rising/falling “stair-type” edges to obtain optimized damping waveform.

Abstract: A circuit structure is provided. The circuit structure may include a first die area including an output gate, a second die area including a circuit and an input gate and a die-to-die interconnect. The input gate may include a transistor. The circuit may be connected between the die-to-die interconnect and a gate region of the transistor. The circuit may include a PMOS transistor and an NMOS transistor. A first source/drain region of the PMOS transistor may be connected to a first source/drain region of the NMOS transistor and the die-to-die interconnect.

Abstract: A stacked semiconductor arrangement is provided. The stacked semiconductor arrangement includes a dynamic pattern generator layer having an electrical component. The arrangement also includes a monitoring layer configured to evaluate electrical performance of the electrical component.

Abstract: Devices and methods are provided for monitoring a transient time in a device under test. A circuit includes a transient edge clipper circuit electrically coupled to the device under test. The transient edge clipper circuit is configured to remove voltage levels of a voltage waveform of the device under test which exceed a threshold range to generate a clipped voltage waveform. The circuit also includes logic circuitry electrically coupled to the transient edge clipper circuit. The logic circuitry is configured to generate a time delayed pulse signal representation of the clipped voltage waveform by injecting a predetermined time delay. The circuit also includes a converter circuit electrically coupled to the logic circuitry. The converter circuit is configured to generate a current signal based on the pulse signal representations.

Abstract: Devices and methods are provided for monitoring a transient time in a device under test. A circuit includes a transient edge clipper circuit electrically coupled to the device under test. The transient edge clipper circuit is configured to remove voltage levels of a voltage waveform of the device under test which exceed a threshold range to generate a clipped voltage waveform. The circuit also includes logic circuitry electrically coupled to the transient edge clipper circuit. The logic circuitry is configured to generate a time delayed pulse signal representation of the clipped voltage waveform by injecting a predetermined time delay. The circuit also includes a converter circuit electrically coupled to the logic circuitry. The converter circuit is configured to generate a current signal based on the pulse signal representations.

Abstract: The present disclosure provides a method for operating a dynamic pattern generator (DPG) having a mirror array. The method comprises receiving a clock signal, determining a time delay based on the period of the clock signal, determining a first clock signal for toggling a first group of mirror cells in the mirror array, determining a second clock signal, lagging behind the first clock signal by the time delay, for toggling a second group of mirror cells in the mirror array, toggling the first group of mirror cells in the mirror array in response to the first clock signal, and toggling the second group of the mirror cells in the mirror array in response to the second clock signal.

Abstract: A de-serialization circuit includes a clock generation circuit, a first and a second latch circuit. The clock generation circuit is configured to generate a set of phase clock signals based on a first clock signal and a control signal. Each phase clock signal of the set of phase clock signals being offset from adjacent phase clock signals of the set of phase clock signals by a phase value. The first latch circuit is configured to generate a first set of data signals based on the set of phase clock signals and an input data signal. The second latch circuit is configured to generate a second set of data signals based on a first phase clock signal of the set of phase clock signals and the first set of data signals. Each signal of the second set of data signals being aligned with each other, wherein the first clock signal is non-continuous.